diff options
| author | macro.wave.z@gmail.com <macro.wave.z@gmail.com> | 2016-12-08 11:58:23 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-12-15 11:57:35 -0800 |
| commit | 5cc8d6682f6bb2934f5303786af6c57e68613a79 (patch) | |
| tree | 987170300856489cc79b8479830e814b6cfdb6c9 /arch/arm/include | |
| parent | df88cb3b91019e7d7293c73b01a5913a02be9c32 (diff) | |
ARMv8: Enable SMC instruction
PSCI implementation needs the SMC instruction to be enabled.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/macro.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 2553e3e349..e1916f7705 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -182,11 +182,17 @@ lr .req x30 /* * The next lower exception level is AArch64, 64bit EL2 | HCE | - * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1. + * RES1 (Bits[5:4]) | Non-secure EL0/EL1. + * and the SMD depends on requirements. */ +#ifdef CONFIG_ARMV8_PSCI + ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ + SCR_EL3_RES1 | SCR_EL3_NS_EN) +#else ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\ SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\ SCR_EL3_NS_EN) +#endif msr scr_el3, \tmp /* Return to the EL2_SP2 mode from EL3 */ |