ARM: Tegra210: Add support to common Tegra source/config files

Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

6 files changed, 45 insertions, 14 deletions

diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h
index ca40e4e0bc..76773b7ec7 100644
--- a/arch/arm/include/asm/arch-tegra/ap.h
+++ b/arch/arm/include/asm/arch-tegra/ap.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010-2011
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -24,8 +24,6 @@
 #define PG_UP_TAG_0_PID_CPU	0x55555555	/* CPU aka "a9" aka "mpcore" */
 #define PG_UP_TAG_0		0x0
 
-#define CORESIGHT_UNLOCK	0xC5ACCE55;
-
 /* AP base physical address of internal SRAM */
 #define NV_PA_BASE_SRAM		0x40000000
 
@@ -66,7 +64,7 @@ int tegra_get_sku_info(void);
 /* Do any chip-specific cache config */
 void config_cache(void);
 
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 /* Do chip-specific vpr config */
 void config_vpr(void);
 #else
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index de50e08201..f69026002b 100644
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -48,6 +48,7 @@ enum {
 	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
 	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W */
 	TEGRA_CLK_SOURCES_X	= 32,	/* Number of ppl clock sources X */
+	TEGRA_CLK_SOURCES_Y	= 18,	/* Number of ppl clock sources Y */
 };
 
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
@@ -94,7 +95,15 @@ struct clk_rst_ctlr {
 	uint crc_rst_dev_x_set;		/* _RST_DEV_X_SET_0,	0x290 */
 	uint crc_rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,	0x294 */
 
-	uint crc_reserved21[23];	/* _reserved_21,	0x298-2f0 */
+	uint crc_clk_out_enb_y;		/* _CLK_OUT_ENB_Y_0,	0x298 */
+	uint crc_clk_enb_y_set;		/* _CLK_ENB_Y_SET_0,	0x29c */
+	uint crc_clk_enb_y_clr;		/* _CLK_ENB_Y_CLR_0,	0x2a0 */
+
+	uint crc_rst_devices_y;		/* _RST_DEVICES_Y_0,	0x2a4 */
+	uint crc_rst_dev_y_set;		/* _RST_DEV_Y_SET_0,	0x2a8 */
+	uint crc_rst_dev_y_clr;		/* _RST_DEV_Y_CLR_0,	0x2ac */
+
+	uint crc_reserved21[17];	/* _reserved_21,	0x2b0-2f0 */
 
 	uint crc_dfll_base;		/* _DFLL_BASE_0,	0x2f4 */
 
@@ -136,7 +145,7 @@ struct clk_rst_ctlr {
 	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
 	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
 	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
-	/* Additional (T114) registers */
+	/* Additional (T114+) registers */
 	uint crc_rst_cpug_cmplx_set;	/* _RST_CPUG_CMPLX_SET_0,  0x450 */
 	uint crc_rst_cpug_cmplx_clr;	/* _RST_CPUG_CMPLX_CLR_0,  0x454 */
 	uint crc_rst_cpulp_cmplx_set;	/* _RST_CPULP_CMPLX_SET_0, 0x458 */
@@ -207,9 +216,18 @@ struct clk_rst_ctlr {
 	u32 _rsv32_1[7];		/*                      0x574-58c */
 	struct clk_pll_simple plldp;	/* _PLLDP_BASE, 0x590 _PLLDP_MISC */
 	u32 crc_plldp_ss_cfg;		/* _PLLDP_SS_CFG, 0x598 */
-	u32 _rsrv32_2[25];
-	/* Tegra124 */
-	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
+
+	/* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
+	uint _rsrv32_2[25];			/* _0x59C - 0x5FC */
+	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
+
+	/* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
+	uint crc_reserved61[5];	/* _reserved_61, 0x680 - 0x690 */
+	/*
+	 * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
+	 * two later if PLLA1 is needed, but for now this is cleaner.
+	 */
+	uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
 };
 
 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
@@ -233,6 +251,8 @@ struct clk_rst_ctlr {
 
 #define PLL_DIVP_SHIFT		20
 #define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
+/* Special case for T210 PLLU DIVP */
+#define PLLU_DIVP_SHIFT		16
 
 #define PLL_DIVN_SHIFT		8
 #define PLL_DIVN_MASK		(0x3ffU << PLL_DIVN_SHIFT)
@@ -261,6 +281,12 @@ struct clk_rst_ctlr {
 #define PLL_LFCON_SHIFT		4
 #define PLL_LFCON_MASK		(15U << PLL_LFCON_SHIFT)
 
+/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
+#define PLLU_KVCO_SHIFT		24
+#define PLLU_KVCO_MASK		(3U << PLLU_KVCO_SHIFT)
+#define PLLU_KCP_SHIFT		25
+#define PLLU_KCP_MASK		(1U << PLLU_KCP_SHIFT)
+
 #define PLLU_VCO_FREQ_SHIFT	20
 #define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
 
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
index 7a86acb1b2..695f3e6fba 100644
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ b/arch/arm/include/asm/arch-tegra/gp_padctrl.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010-2012
+ *  (C) Copyright 2010-2015
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -21,5 +21,6 @@
 #define CHIPID_TEGRA30			0x30
 #define CHIPID_TEGRA114			0x35
 #define CHIPID_TEGRA124			0x40
+#define CHIPID_TEGRA210			0x21
 
 #endif	/* _TEGRA_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pmc.h b/arch/arm/include/asm/arch-tegra/pmc.h
index 1dd3154fbc..66c0879765 100644
--- a/arch/arm/include/asm/arch-tegra/pmc.h
+++ b/arch/arm/include/asm/arch-tegra/pmc.h
@@ -1,5 +1,5 @@
 /*
- *  (C) Copyright 2010,2011,2014
+ *  (C) Copyright 2010-2015
  *  NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -294,6 +294,7 @@ struct pmc_ctlr {
 #define CRAIL		0
 #define CE0		14
 #define C0NC		15
+#define SOR		17
 
 #define PMC_XOFS_SHIFT	1
 #define PMC_XOFS_MASK	(0x3F << PMC_XOFS_SHIFT)
@@ -303,7 +304,7 @@ struct pmc_ctlr {
 #define TIMER_MULT_MASK		(3 << TIMER_MULT_SHIFT)
 #define TIMER_MULT_CPU_SHIFT	2
 #define TIMER_MULT_CPU_MASK	(3 << TIMER_MULT_CPU_SHIFT)
-#elif defined(CONFIG_TEGRA124)
+#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 #define TIMER_MULT_SHIFT	0
 #define TIMER_MULT_MASK		(7 << TIMER_MULT_SHIFT)
 #define TIMER_MULT_CPU_SHIFT	3
@@ -314,7 +315,7 @@ struct pmc_ctlr {
 #define MULT_2			1
 #define MULT_4			2
 #define MULT_8			3
-#if defined(CONFIG_TEGRA124)
+#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
 #define MULT_16			4
 #endif
 
diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index d63af0e5fd..b6c7cabc9a 100644
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2010,2011
+ * (C) Copyright 2010-2015
  * NVIDIA Corporation <www.nvidia.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -74,6 +74,7 @@ enum {
 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
 	SKU_ID_T114_1		= 0x01,
 	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
+	SKU_ID_T210_ENG		= 0x00, /* unfused value TBD */
 };
 
 /*
@@ -88,6 +89,7 @@ enum {
 	TEGRA_SOC_T30,
 	TEGRA_SOC_T114,
 	TEGRA_SOC_T124,
+	TEGRA_SOC_T210,
 
 	TEGRA_SOC_CNT,
 	TEGRA_SOC_UNKNOWN	= -1,
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index c817088fa5..f400c01a39 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -266,6 +266,9 @@ struct usb_ctlr {
 
 /* USBx_UTMIP_BIAS_CFG1_0 */
 #define UTMIP_FORCE_PDTRK_POWERDOWN		1
+#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT	8
+#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK	\
+				(0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
 #define UTMIP_BIAS_PDTRK_COUNT_MASK		\
 				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)