diff options
| author | Simon Glass <sjg@chromium.org> | 2015-04-14 21:03:34 -0600 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-05-13 09:24:09 -0700 |
| commit | 96e82a253a4c3a122de5023d9ca5fe04d9e19502 (patch) | |
| tree | c6fa11ecd9601ba006d23c83b060a99151029af6 /arch/arm/include | |
| parent | 7bb6199bd6c95c89bb9b8e2e2890223e2bca6595 (diff) | |
tegra124: clock: Add display clocks and functions
Add functions to provide access to the display clocks on Tegra124 including
setting the clock rate for an EDP display.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/clk_rst.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra124/clock-tables.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-tegra124/clock.h | 21 |
3 files changed, 35 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h index 7d28e16f1c..de50e08201 100644 --- a/arch/arm/include/asm/arch-tegra/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra/clk_rst.h @@ -202,9 +202,13 @@ struct clk_rst_ctlr { uint crc_reserved52[1]; /* _reserved_52, 0x554 */ uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ - - /* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */ - uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ + u32 _rsv32[4]; /* 0x560-0x56c */ + u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ + u32 _rsv32_1[7]; /* 0x574-58c */ + struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */ + u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + u32 _rsrv32_2[25]; + /* Tegra124 */ uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ }; @@ -440,4 +444,9 @@ enum { #define PLLX_IDDQ_SHIFT 3 #define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT) +/* CLK_RST_PLLDP_SS_CFG */ +#define PLLDP_SS_CFG_CLAMP (1 << 22) +#define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24) +#define PLLDP_SS_CFG_DITHER (1 << 28) + #endif /* _TEGRA_CLK_RST_H_ */ diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h index daf9a2b351..7005855999 100644 --- a/arch/arm/include/asm/arch-tegra124/clock-tables.h +++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h @@ -25,6 +25,7 @@ enum clock_id { CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, CLOCK_ID_EPCI, CLOCK_ID_SFROM32KHZ, + CLOCK_ID_DP, /* Special for Tegra124 */ /* These are the base clocks (inputs to the Tegra SoC) */ CLOCK_ID_32KHZ, @@ -424,7 +425,7 @@ enum periphc_internal_id { /* 0x58 */ PERIPHC_58h, - PERIPHC_59h, + PERIPHC_SOR, PERIPHC_5ah, PERIPHC_5bh, PERIPHC_SATAOOB, diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h index 8e65086252..e202cc5a7f 100644 --- a/arch/arm/include/asm/arch-tegra124/clock.h +++ b/arch/arm/include/asm/arch-tegra124/clock.h @@ -16,6 +16,27 @@ #define OSC_FREQ_SHIFT 28 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) +/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ +#define SOR0_CLK_SEL0 (1 << 14) +#define SOR0_CLK_SEL1 (1 << 15) + int tegra_plle_enable(void); +void clock_sor_enable_edp_clock(void); + +/** + * clock_set_display_rate() - Set the display clock rate + * + * @frequency: the requested PLLD frequency + * + * Return the PLLD frequenc (which may not quite what was requested), or 0 + * on failure + */ +u32 clock_set_display_rate(u32 frequency); + +/** + * clock_set_up_plldp() - Set up the EDP clock ready for use + */ +void clock_set_up_plldp(void); + #endif /* _TEGRA124_CLOCK_H_ */ |