diff options
| author | Tom Warren <twarren@nvidia.com> | 2019-06-03 16:06:34 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2020-04-02 14:30:01 -0700 |
| commit | a482f32992230d8bdae2caa72056ab7d9208d5f0 (patch) | |
| tree | 02b8009a11d357044536905c5eeb79e8d1ceba3e /arch/arm/include | |
| parent | 5e965e814067e7539943bbaeb47d7bf9738a701b (diff) | |
mmc: t210: Fix 'bad' SD-card clock when doing 400KHz card detect
According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is <= 400KHz. Note that as far as I can
tell, the other requests for clocks in the Tegra MMC driver result in
valid SD clocks.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/tegra_mmc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index a8bfa466c0..70dcf4aa66 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -130,9 +130,9 @@ struct tegra_mmc { /* SDMMC1/3 settings from SDMMCx Initialization Sequence of TRM */ #define MEMCOMP_PADCTRL_VREF 7 #define AUTO_CAL_ENABLE (1 << 29) -#if defined(CONFIG_TEGRA210) #define AUTO_CAL_ACTIVE (1 << 31) #define AUTO_CAL_START (1 << 31) +#if defined(CONFIG_TEGRA210) #define AUTO_CAL_PD_OFFSET (0x7D << 8) #define AUTO_CAL_PU_OFFSET (0 << 0) #define IO_TRIM_BYPASS_MASK (1 << 2) |