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authorPatrice Chotard <patrice.chotard@st.com>2018-02-07 10:44:50 +0100
committerTom Rini <trini@konsulko.com>2018-03-13 21:45:37 -0400
commitaa5e3e22f4d648c09b6b63eac8eec8d7a2fc2994 (patch)
treea7e69e428ecec4158442686b671a94f788023114 /arch/arm/include
parentcd389c03f270636e581a16ba157e37b47ae75d93 (diff)
board: stm32: switch to DM STM32 timer
Use available DM stm32_timer driver instead of dedicated mach-stm32/stm32fx/timer.c. Remove all defines or files previously used for timer usage in arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx Enable DM STM32_TIMER for STM32F4/F7 and H7. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-stm32f4/stm32.h3
-rw-r--r--arch/arm/include/asm/arch-stm32f4/stm32_defs.h15
-rw-r--r--arch/arm/include/asm/arch-stm32f7/gpt.h53
-rw-r--r--arch/arm/include/asm/arch-stm32f7/stm32.h5
-rw-r--r--arch/arm/include/asm/arch-stm32f7/stm32_defs.h15
-rw-r--r--arch/arm/include/asm/arch-stm32f7/stm32_periph.h4
6 files changed, 0 insertions, 95 deletions
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 0449fceced..763b18cb54 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -38,9 +38,6 @@ struct stm32_u_id_regs {
#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10)
#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE)
-#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
-#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
-
#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h b/arch/arm/include/asm/arch-stm32f4/stm32_defs.h
deleted file mode 100644
index 9a967ac38a..0000000000
--- a/arch/arm/include/asm/arch-stm32f4/stm32_defs.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __STM32_DEFS_H__
-#define __STM32_DEFS_H__
-#include <asm/arch/stm32_periph.h>
-
-int clock_setup(enum periph_clock);
-
-#endif
-
diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h b/arch/arm/include/asm/arch-stm32f7/gpt.h
deleted file mode 100644
index b43dc612c8..0000000000
--- a/arch/arm/include/asm/arch-stm32f7/gpt.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _STM32_GPT_H
-#define _STM32_GPT_H
-
-#include <asm/arch/stm32.h>
-
-struct gpt_regs {
- u32 cr1;
- u32 cr2;
- u32 smcr;
- u32 dier;
- u32 sr;
- u32 egr;
- u32 ccmr1;
- u32 ccmr2;
- u32 ccer;
- u32 cnt;
- u32 psc;
- u32 arr;
- u32 reserved;
- u32 ccr1;
- u32 ccr2;
- u32 ccr3;
- u32 ccr4;
- u32 reserved1;
- u32 dcr;
- u32 dmar;
- u32 tim2_5_or;
-};
-
-struct gpt_regs *const gpt1_regs_ptr =
- (struct gpt_regs *)TIM2_BASE;
-
-/* Timer control1 register */
-#define GPT_CR1_CEN BIT(0)
-#define GPT_MODE_AUTO_RELOAD BIT(7)
-
-/* Auto reload register for free running config */
-#define GPT_FREE_RUNNING 0xFFFFFFFF
-
-/* Timer, HZ specific defines */
-#define CONFIG_STM32_HZ 1000
-
-/* Timer Event Generation registers */
-#define TIM_EGR_UG BIT(0)
-
-#endif
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index f54e6f1955..40df891426 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -25,7 +25,6 @@
#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000)
#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000)
-#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
#define USART2_BASE (APB1_PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1_PERIPH_BASE + 0x4800)
#define PWR_BASE (APB1_PERIPH_BASE + 0x7000)
@@ -45,7 +44,6 @@
#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000)
#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400)
#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800)
-#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800)
#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
@@ -59,9 +57,6 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
#define STM32_BUS_MASK GENMASK(31, 16)
-#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-
-
void stm32_flash_latency_cfg(int latency);
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_defs.h b/arch/arm/include/asm/arch-stm32f7/stm32_defs.h
deleted file mode 100644
index 9a967ac38a..0000000000
--- a/arch/arm/include/asm/arch-stm32f7/stm32_defs.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __STM32_DEFS_H__
-#define __STM32_DEFS_H__
-#include <asm/arch/stm32_periph.h>
-
-int clock_setup(enum periph_clock);
-
-#endif
-
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
index 7b8f66a034..38d4ade13d 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32_periph.h
@@ -20,8 +20,4 @@ enum periph_id {
PERIPH_ID_QUADSPI = 92,
};
-enum periph_clock {
- TIMER2_CLOCK_CFG,
-};
-
#endif /* __ASM_ARM_ARCH_PERIPH_H */