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| author | Tom Rini <trini@konsulko.com> | 2019-05-05 12:25:39 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-05-05 12:25:39 -0400 |
| commit | abad176da14c576b5126484b03cba73a3b2c6f16 (patch) | |
| tree | 1baba7f9058acf8e41a043e6ce0f08dd1b94f644 /arch/arm/include | |
| parent | 86f578ee85a697afb980233312f9aac1d98816df (diff) | |
| parent | 9337a08768dfa0a006382f1d05cf69b5f67f7844 (diff) | |
Merge branch '2019-05-05-master-imports'
- Various assorted fixes
- btrfs zstd compression support
- Enable hardware DDR levelling on am43xx platforms.
- pl310 cache controller driver
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/pl310.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h index b83978b1cc..f69e9e45f8 100644 --- a/arch/arm/include/asm/pl310.h +++ b/arch/arm/include/asm/pl310.h @@ -18,6 +18,9 @@ #define L310_SHARED_ATT_OVERRIDE_ENABLE (1 << 22) #define L310_AUX_CTRL_DATA_PREFETCH_MASK (1 << 28) #define L310_AUX_CTRL_INST_PREFETCH_MASK (1 << 29) +#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) +#define L310_LATENCY_CTRL_RD(n) ((n) << 4) +#define L310_LATENCY_CTRL_WR(n) ((n) << 8) #define L2X0_CACHE_ID_PART_MASK (0xf << 6) #define L2X0_CACHE_ID_PART_L310 (3 << 6) |