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authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>2015-06-26 18:05:07 +0530
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2015-07-31 01:38:12 +0200
commitdad17fd51027ad02ac8f02deed186d08109d61fd (patch)
treeef4f7170fbea6995436173711b2d23e65b07bdb0 /arch/arm/include
parentcc35734358540a1bbaf042fdf9f4cb2de17389ed (diff)
armv8: caches: Added routine to set non cacheable region
Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/system.h29
1 files changed, 19 insertions, 10 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 760e8ab1c8..868ea54b4f 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -15,9 +15,15 @@
#define CR_EE (1 << 25) /* Exception (Big) Endian */
#define PGTABLE_SIZE (0x10000)
+/* 2MB granularity */
+#define MMU_SECTION_SHIFT 21
#ifndef __ASSEMBLY__
+enum dcache_option {
+ DCACHE_OFF = 0x3,
+};
+
#define isb() \
({asm volatile( \
"isb" : : : "memory"); \
@@ -265,16 +271,6 @@ enum {
#endif
/**
- * Change the cache settings for a region.
- *
- * \param start start address of memory region to change
- * \param size size of memory region to change
- * \param option dcache option to select
- */
-void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
- enum dcache_option option);
-
-/**
* Register an update to the page tables, and flush the TLB
*
* \param start start address of update in page table
@@ -295,4 +291,17 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* CONFIG_ARM64 */
+#ifndef __ASSEMBLY__
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start start address of memory region to change
+ * \param size size of memory region to change
+ * \param option dcache option to select
+ */
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+ enum dcache_option option);
+
+#endif /* __ASSEMBLY__ */
+
#endif