diff options
| author | Akshay Saraswat <akshay.s@samsung.com> | 2014-05-26 19:20:08 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-06-13 17:05:14 +0900 |
| commit | ed32522fe048f9edcb3269c8d5af79c6e8c6daea (patch) | |
| tree | 61a005141819f84aa56f8588f87cc78f575f42d6 /arch/arm/include | |
| parent | c9334fcda90652e2f8c49f4517b728ebc6f5f623 (diff) | |
Exynos5420: DMC: Add software read leveling
Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/dmc.h | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/power.h | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h b/arch/arm/include/asm/arch-exynos/dmc.h index d78536d2df..ec3f9b6ee1 100644 --- a/arch/arm/include/asm/arch-exynos/dmc.h +++ b/arch/arm/include/asm/arch-exynos/dmc.h @@ -467,6 +467,9 @@ enum mem_manuf { /* PHY_CON1 register fields */ #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0 +/* PHY_CON4 rgister fields */ +#define PHY_CON10_CTRL_OFFSETR3 (1 << 24) + /* PHY_CON12 register fields */ #define PHY_CON12_CTRL_START_POINT_SHIFT 24 #define PHY_CON12_CTRL_INC_SHIFT 16 diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index a4b41adca9..4f2447b3f8 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -906,8 +906,8 @@ struct exynos5420_power { unsigned int sysip_dat3; unsigned char res11[0xe0]; unsigned int pmu_spare0; - unsigned int pmu_spare1; - unsigned int pmu_spare2; + unsigned int pmu_spare1; /* Store PHY0_CON4 for read leveling */ + unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */ unsigned int pmu_spare3; unsigned char res12[0x4]; unsigned int cg_status0; |