diff options
| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 14:08:28 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-03-04 10:09:00 -0700 |
| commit | f2c60eed513ecc142e0a39373d5c16a14f976d6d (patch) | |
| tree | 55ada1683e0fd84d9d3307c1cd4ebaa80143c73e /arch/arm/include | |
| parent | b2cd3d810387095e525522de6cae2716f4c20870 (diff) | |
ARM: tegra: pinmux: support hsm/schmitt on pins
T210 support HSM and Schmitt options in the pinmux register (previous
chips placed these options in the drive group register). Update the
code to handle this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/pinmux.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index 1562fa410c..d87da10e0d 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -74,7 +74,7 @@ enum pmux_lpmd { }; #endif -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT +#if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) /* Defines whether a pin group cfg's schmidt is enabled or not */ enum pmux_schmt { PMUX_SCHMT_DISABLE = 0, @@ -83,7 +83,7 @@ enum pmux_schmt { }; #endif -#ifdef TEGRA_PMX_GRPS_HAVE_HSM +#if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) /* Defines whether a pin group cfg's high-speed mode is enabled or not */ enum pmux_hsm { PMUX_HSM_DISABLE = 0, @@ -119,6 +119,12 @@ struct pmux_pingrp_config { u32 rcv_sel:2; /* select between High and Normal */ /* VIL/VIH receivers */ #endif +#ifdef TEGRA_PMX_PINS_HAVE_SCHMT + u32 schmt:2; /* schmitt enable */ +#endif +#ifdef TEGRA_PMX_PINS_HAVE_HSM + u32 hsm:2; /* high-speed mode enable */ +#endif }; #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING |