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authorMarek Vasut <marex@denx.de>2019-02-19 01:43:51 +0100
committerTom Rini <trini@konsulko.com>2019-02-28 14:21:46 -0500
commit86dc480d73776e6628ea39a5429f160ffdc2ec85 (patch)
treed0355d8f8bf5c4704f7413dcdeca8e1449d908d9 /arch/arm/lib/cache-pl310.c
parentb8b88e6aff3ea7346a39bfbb27124b275ce56666 (diff)
ARM: cache: Fix incorrect bitwise operation
The loop implemented in the code is supposed to check whether the PL310 operation register has any bit from the mask set. Currently, the code checks whether the PL310 operation register has any bit set AND whether the mask is non-zero, which is incorrect. Fix the conditional. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Tom Rini <trini@konsulko.com> Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot") Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/lib/cache-pl310.c')
-rw-r--r--arch/arm/lib/cache-pl310.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
index 1296ba6efd..bbaaaa4157 100644
--- a/arch/arm/lib/cache-pl310.c
+++ b/arch/arm/lib/cache-pl310.c
@@ -33,7 +33,7 @@ static void pl310_background_op_all_ways(u32 *op_reg)
/* Invalidate all ways */
writel(way_mask, op_reg);
/* Wait for all ways to be invalidated */
- while (readl(op_reg) && way_mask)
+ while (readl(op_reg) & way_mask)
;
pl310_cache_sync();
}