diff options
| author | Ovidiu Panait <ovpanait@gmail.com> | 2020-03-29 20:57:39 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-24 15:17:14 -0400 |
| commit | 586b15bce82a2161dbe71991c14c8c36f5683033 (patch) | |
| tree | 10b508372f5cb670bc22df00e5abc5ca28f9aa77 /arch/arm/lib/cache.c | |
| parent | 4d131cdb6762694fc1a66d6b3e39a82f9ec691cf (diff) | |
common/board_f: Move arm-specific reserve_mmu to arch/arm/lib/cache.c
Move the ARM-specific reserve_mmu definition from common/board_f.c
to arch/arm/lib/cache.c.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/lib/cache.c')
| -rw-r--r-- | arch/arm/lib/cache.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 007d4ebc49..b8e1e340a1 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,8 @@ #include <cpu_func.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; + /* * Flush range from all levels of d-cache/unified-cache. * Affects the range [start, start + size - 1]. @@ -118,3 +120,29 @@ void invalidate_l2_cache(void) isb(); } #endif + +__weak int reserve_mmu(void) +{ +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->relocaddr -= gd->arch.tlb_size; + + /* round down to next 64 kB limit */ + gd->relocaddr &= ~(0x10000 - 1); + + gd->arch.tlb_addr = gd->relocaddr; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* + * Record allocated tlb_addr in case gd->tlb_addr to be overwritten + * with location within secure ram. + */ + gd->arch.tlb_allocated = gd->arch.tlb_addr; +#endif +#endif + + return 0; +} |