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authorBhupesh Sharma <bhupesh.sharma@freescale.com>2015-07-01 09:58:03 +0530
committerYork Sun <yorksun@freescale.com>2015-09-01 21:37:49 -0500
commit3ffa95c283aa45e97d35c033577ab0b67628f426 (patch)
tree10029547191cdabdefcf6d4c2ce70569e1035f79 /arch/arm/lib
parent7fb79e6552c45487ff31d00ef4f54d0e040d457f (diff)
armv8: Add framework for CCN-504 interconnect configuration
This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports. LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/lib')
-rw-r--r--arch/arm/lib/Makefile1
-rw-r--r--arch/arm/lib/ccn504.S61
2 files changed, 62 insertions, 0 deletions
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 31a5c8d77f..51497cc289 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -42,6 +42,7 @@ obj-y += stack.o
ifdef CONFIG_CPU_V7M
obj-y += interrupts_m.o
else ifdef CONFIG_ARM64
+obj-y += ccn504.o
obj-y += gic_64.o
obj-y += interrupts_64.o
else
diff --git a/arch/arm/lib/ccn504.S b/arch/arm/lib/ccn504.S
new file mode 100644
index 0000000000..7570c7b231
--- /dev/null
+++ b/arch/arm/lib/ccn504.S
@@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Extracted from gic_64.S
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+/*************************************************************************
+ *
+ * void ccn504_add_masters_to_dvm(CCI_MN_BASE, CCI_MN_RNF_NODEID_LIST,
+ * CCI_MN_DVM_DOMAIN_CTL_SET);
+ *
+ * Add fully-coherent masters to DVM domain
+ *
+ *************************************************************************/
+ENTRY(ccn504_add_masters_to_dvm)
+ /*
+ * x0: CCI_MN_BASE
+ * x1: CCI_MN_RNF_NODEID_LIST
+ * x2: CCI_MN_DVM_DOMAIN_CTL_SET
+ */
+
+ /* Add fully-coherent masters to DVM domain */
+ ldr x9, [x0, x1]
+ str x9, [x0, x2]
+1: ldr x10, [x0, x2]
+ mvn x11, x10
+ tst x11, x10 /* Wait for domain addition to complete */
+ b.ne 1b
+
+ ret
+ENDPROC(ccn504_add_masters_to_dvm)
+
+/*************************************************************************
+ *
+ * void ccn504_set_qos(CCI_Sx_QOS_CONTROL_BASE, QoS Value);
+ *
+ * Initialize QoS settings for AR/AW override.
+ * Right now, this function sets the same QoS value for all RN-I ports
+ *
+ *************************************************************************/
+ENTRY(ccn504_set_qos)
+ /*
+ * x0: CCI_Sx_QOS_CONTROL_BASE
+ * x1: QoS Value
+ */
+
+ /* Set all RN-I ports to QoS value denoted by x1 */
+ ldr x9, [x0]
+ mov x10, x1
+ orr x9, x9, x10
+ str x9, [x0]
+
+ ret
+ENDPROC(ccn504_set_qos)
+