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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-10-11 01:20:30 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-10-11 01:20:30 +0200 |
| commit | 790af815436bc6a93e4c581840be2419897f23b1 (patch) | |
| tree | 1ba0aaacad86092aea67d3612ae066b33b117619 /arch/arm/lib | |
| parent | d0b3723034aa865b8618428739efe1d98b1a2e2b (diff) | |
| parent | db67801bf92f7fae6131dbc0d387131698fb9490 (diff) | |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/lib')
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3e62d58542..2155fe8187 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank) i++) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) set_section_dcache(i, DCACHE_WRITETHROUGH); +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) + set_section_dcache(i, DCACHE_WRITEALLOC); #else set_section_dcache(i, DCACHE_WRITEBACK); #endif |