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| author | Tom Rini <trini@konsulko.com> | 2017-06-10 18:01:22 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-06-10 18:01:22 -0400 |
| commit | 8cb3ce64f936f5dedbcfc1935c5caf31bb682474 (patch) | |
| tree | bc6cbbacd344ccdac327b4bb7337aa316ad000e0 /arch/arm/lib | |
| parent | 4bdb49a7487d1c46c04e3da3f1f370cde1566aea (diff) | |
| parent | 9620d87259572ef21f0df60988d9a932ca673779 (diff) | |
Merge git://git.denx.de/u-boot-dm
Diffstat (limited to 'arch/arm/lib')
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index e9bbcf5122..cf852c061b 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -129,7 +129,7 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } -#ifdef CONFIG_ARMV7_LPAE +#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4 /* Set up 4 PTE entries pointing to our 4 1GB page tables */ for (i = 0; i < 4; i++) { u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4)); @@ -147,7 +147,7 @@ static inline void mmu_setup(void) #endif if (is_hyp()) { - /* Set HCTR to enable LPAE */ + /* Set HTCR to enable LPAE */ asm volatile("mcr p15, 4, %0, c2, c0, 2" : : "r" (reg) : "memory"); /* Set HTTBR0 */ @@ -172,6 +172,15 @@ static inline void mmu_setup(void) : : "r" (MEMORY_ATTRIBUTES) : "memory"); } #elif defined(CONFIG_CPU_V7) + if (is_hyp()) { + /* Set HTCR to disable LPAE */ + asm volatile("mcr p15, 4, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } else { + /* Set TTBCR to disable LPAE */ + asm volatile("mcr p15, 0, %0, c2, c0, 2" + : : "r" (0) : "memory"); + } /* Set TTBR0 */ reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |