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authorMarek Vasut <marex@denx.de>2014-09-15 02:44:36 +0200
committerMarek Vasut <marex@denx.de>2014-10-06 17:40:21 +0200
commitff7e9700eda14ccf8ebe399d3831ef266e743c2d (patch)
tree9bd837293a6b70f56f4d5ea02d67d8236590b8dc /arch/arm/lib
parentbe9f643ae6aa9044c60fe80e3a2c10be8371c692 (diff)
arm: cache: Add support for write-allocate D-Cache
Add configuration for the write-allocate mode of L1 D-Cache on ARM. This is needed for D-Cache operation on Cortex-A9 on the SoCFPGA . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Diffstat (limited to 'arch/arm/lib')
-rw-r--r--arch/arm/lib/cache-cp15.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 3e62d58542..2155fe8187 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -73,6 +73,8 @@ __weak void dram_bank_mmu_setup(int bank)
i++) {
#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
set_section_dcache(i, DCACHE_WRITETHROUGH);
+#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+ set_section_dcache(i, DCACHE_WRITEALLOC);
#else
set_section_dcache(i, DCACHE_WRITEBACK);
#endif