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authorWenyou Yang <wenyou.yang@atmel.com>2017-03-23 12:44:37 +0800
committerSimon Glass <sjg@chromium.org>2017-04-13 14:44:50 -0600
commit9319a756fffb0aae21adcd7caf8674411a22c165 (patch)
treebdab37d1a13b25e92d18aba284a5869512e5be29 /arch/arm/mach-at91/include/mach/at91_pio.h
parent2dc63f73678c18831efce3ec1a383375aa5423f1 (diff)
pinctrl: at91: add pinctrl driver
AT91 PIO controller is a combined gpio-controller, pin-mux and pin-config module. The peripheral's pins are assigned through per-pin based muxing logic. Each SoC will have to describe the its limitation and pin configuration via device tree. This will allow to do not need to touch the C code when adding new SoC if the IP version is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-at91/include/mach/at91_pio.h')
-rw-r--r--arch/arm/mach-at91/include/mach/at91_pio.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_pio.h b/arch/arm/mach-at91/include/mach/at91_pio.h
index 946f076714..4840a2b8f2 100644
--- a/arch/arm/mach-at91/include/mach/at91_pio.h
+++ b/arch/arm/mach-at91/include/mach/at91_pio.h
@@ -109,7 +109,11 @@ typedef struct at91_port {
u32 wpsr; /* 0xE8 Write Protect Status Register */
u32 reserved11[5]; /* */
u32 schmitt; /* 0x100 Schmitt Trigger Register */
- u32 reserved12[63];
+ u32 reserved12[4]; /* 0x104 ~ 0x110 */
+ u32 driver1; /* 0x114 I/O Driver Register1(AT91SAM9x5's driver1) */
+ u32 driver12; /* 0x118 I/O Driver Register12(AT91SAM9x5's driver2 or SAMA5D3x's driver1 ) */
+ u32 driver2; /* 0x11C I/O Driver Register2(SAMA5D3x's driver2) */
+ u32 reserved13[12]; /* 0x120 ~ 0x14C */
} at91_port_t;
typedef union at91_pio {