diff options
| author | Wenyou Yang <wenyou.yang@microchip.com> | 2017-09-05 18:30:07 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-09-14 16:02:29 -0400 |
| commit | e7c831543ab8deeb1eb4bf4d13d59f55a268865e (patch) | |
| tree | aaf4d9198f4f0eb024518b420d8229486b175976 /arch/arm/mach-at91/include/mach | |
| parent | 0712b672d2a1f9a156c489b4dd7ce8354c2b3e1f (diff) | |
clk: at91: utmi: Set the reference clock frequency
By default, it is assumed that the UTMI clock is generated from
a 12 MHz reference clock (MAINCK). If it's not the case, the FREQ
field of the SFR_UTMICKTRIM has to be updated to generate the UTMI
clock in the proper way.
The UTMI clock has a fixed rate of 480 MHz. In fact, there is no
multiplier we can configure. The multiplier is managed internally,
depending on the reference clock frequency, to achieve the target
of 480 MHz.
The patch is cloned from the patch of mailing-list:
[PATCH v2] clk: at91: utmi: set the mainck rate
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
[trini: Depend on SPL_DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-at91/include/mach')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5_sfr.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index b805a2c934..965631aad7 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -28,6 +28,9 @@ struct atmel_sfr { u32 l2cc_hramc; /* 0x58 */ }; +/* Register Mapping*/ +#define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ + /* Bit field in DDRCFG */ #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 #define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 @@ -56,6 +59,8 @@ struct atmel_sfr { #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) +#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) + /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 |