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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2015-02-20 17:04:03 +0900
committerTom Rini <trini@ti.com>2015-02-21 08:23:51 -0500
commit620118403e1521b4c883848a84d2fb68e3fa1aa0 (patch)
tree880f15ded4ea034088c4155d56a4846e8edc54f0 /arch/arm/mach-at91/phy.c
parent01f14456306c84f9bcd3945a10c98ae50e30542a (diff)
ARM: at91: collect SoC sources into mach-at91
This commit moves source files as follows: arch/arm/cpu/arm920t/at91/* -> arch/arm/mach-at91/arm920t/* arch/arm/cpu/arm926ejs/at91/* -> arch/arm/mach-at91/arm926ejs/* arch/arm/cpu/armv7/at91/* -> arch/arm/mach-at91/armv7/* arch/arm/cpu/at91-common/* -> arch/arm/mach-at91/* Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.co>
Diffstat (limited to 'arch/arm/mach-at91/phy.c')
-rw-r--r--arch/arm/mach-at91/phy.c57
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c
new file mode 100644
index 0000000000..2cba7169e4
--- /dev/null
+++ b/arch/arm/mach-at91/phy.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <watchdog.h>
+
+void at91_phy_reset(void)
+{
+ unsigned long erstl;
+ unsigned long start = get_timer(0);
+ unsigned long const timeout = 1000; /* 1000ms */
+ at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+ erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+ /*
+ * Need to reset PHY -> 500ms reset
+ * Reset PHY by pulling the NRST line for 500ms to low. To do so
+ * disable user reset for low level on NRST pin and poll the NRST
+ * level in reset status register.
+ */
+ writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+ AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+ writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+ /* Wait for end of hardware reset */
+ while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
+ /* avoid shutdown by watchdog */
+ WATCHDOG_RESET();
+ mdelay(10);
+
+ /* timeout for not getting stuck in an endless loop */
+ if (get_timer(start) >= timeout) {
+ puts("*** ERROR: Timeout waiting for PHY reset!\n");
+ break;
+ }
+ };
+
+ /* Restore NRST value */
+ writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+}