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| author | Tom Rini <trini@konsulko.com> | 2015-11-05 07:46:45 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-11-05 07:46:45 -0500 |
| commit | 60b25259a5540686add02cf6c94cd7494a3e2d23 (patch) | |
| tree | abccf513238a9bab314b4672858512801da85580 /arch/arm/mach-exynos/dmc_init_ddr3.c | |
| parent | 1674942ad777bc1ae26fe93684836dcd8820f47f (diff) | |
| parent | 58cb44cf6623faeebd9b04ac44cf11d2eb39ea36 (diff) | |
Merge git://git.denx.de/u-boot-samsung
Diffstat (limited to 'arch/arm/mach-exynos/dmc_init_ddr3.c')
| -rw-r--r-- | arch/arm/mach-exynos/dmc_init_ddr3.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index 7c0b12ae51..25a9df9364 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -20,8 +20,8 @@ #define TIMEOUT_US 10000 #define NUM_BYTE_LANES 4 #define DEFAULT_DQS 8 -#define DEFAULT_DQS_X4 (DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ - || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0) +#define DEFAULT_DQS_X4 ((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \ + || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0)) #ifdef CONFIG_EXYNOS5250 static void reset_phy_ctrl(void) @@ -856,10 +856,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) */ val = readl(&drex0->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex0->concontrol); + writel(val, &drex0->concontrol); val = readl(&drex1->concontrol); val |= CONCONTROL_UPDATE_MODE; - writel(val , &drex1->concontrol); + writel(val, &drex1->concontrol); return 0; } |