diff options
| author | Trent Piepho <tpiepho@impinj.com> | 2019-03-27 23:50:09 +0000 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-04-23 17:57:27 -0400 |
| commit | b4353b371322b54d8effd8737e3f7ba021950180 (patch) | |
| tree | 361d800d7173ed5302d748627335a645c3f66ee4 /arch/arm/mach-exynos/exynos5_setup.h | |
| parent | 4c6be01c2719e78cd7ff257dd65a666623566863 (diff) | |
bootm: Simplying cache flush code
The cache flush of the kernel load area needs to be aligned outward to
the DMA cache alignment. The operations are simpler if we think of this
as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and
aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find
the length of the flushed region by subtracting the former from the
latter.
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-exynos/exynos5_setup.h')
0 files changed, 0 insertions, 0 deletions