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authorStefan Agner <stefan.agner@toradex.com>2018-06-26 11:10:52 +0200
committerStefano Babic <sbabic@denx.de>2018-07-23 10:56:38 +0200
commita19797b22cbc955ade2ef59c78fbdeea866285a9 (patch)
tree0b2428a9ce10635390975773eec5eed9b1d13c08 /arch/arm/mach-highbank
parente38adcecca4731acaa51b37b00ee5feee55b6b85 (diff)
colibri_imx7: improve DDR3 timing
This makes sure that all Colibri iMX7 modules work with the same timing. The changes are: - Disable ODT on read (JEDEC standard JESD79-3F says in chapter 5.2.3 ODT during Reads: "As the DDR3 SDRAM can not terminate and drive at the same time, RTT must be disabled at least half a clock cycle..." and also MX7D SABRESD is disabling it) This alone fixed memory issues for two Colibri iMX7 1GB modules which showed issues before - Make sure tRFC(min) is at least 260ns - Make sure tRC is >50.625ns - tRP needs to be >13.125ns, we can lower from 18.75ns to 15ns - tFAW is not relevant, leave at reset Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
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