diff options
| author | Fabio Estevam <festevam@gmail.com> | 2019-07-12 09:32:23 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-11-03 13:16:51 +0100 |
| commit | fa64df460267d6189951c23f90b7e93c0f852ead (patch) | |
| tree | b1b7622e6a6e67228bc73eb8fb3321e94b02a1e3 /arch/arm/mach-imx/mx6/clock.c | |
| parent | 1be51fed567748a1103d69102b0da2af9f699618 (diff) | |
mx6: clock: Introduce disable_ipu_clock()
Introduce disable_ipu_clock(). This is done in preparation for
configuring the NoC registers on i.MX6QP in SPL.
Afer the NoC registers are set the IPU clocks can be disabled.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/mx6/clock.c')
| -rw-r--r-- | arch/arm/mach-imx/mx6/clock.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index 9d432b4104..6a9e673ca2 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1287,6 +1287,18 @@ void enable_ipu_clock(void) setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); } } + +void disable_ipu_clock(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_MASK); + + if (is_mx6dqp()) { + clrbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); + clrbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + } +} #endif #ifndef CONFIG_SPL_BUILD |