Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.01
-----------------

- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support

6 files changed, 121 insertions, 68 deletions

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 181c715be3..5ce5a180e8 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -217,6 +217,7 @@ u32 get_cpu_rev(void)
 					readl((void __iomem *)ROM_VERSION_A0);
 				if (rom_version != CHIP_REV_1_0) {
 					rom_version = readl((void __iomem *)ROM_VERSION_B0);
+					rom_version &= 0xff;
 					if (rom_version == CHIP_REV_2_0)
 						reg = CHIP_REV_2_0;
 				}
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 607210520f..ef816a24ff 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000
 	select DM
 	select DM_THERMAL
 	select MX6SX
+	select SUPPORT_SPL
 	imply CMD_DM
 
 config TARGET_WANDBOARD
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 926718b49c..b8aaf3ef01 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -24,12 +24,6 @@
 #include <imx_thermal.h>
 #include <mmc.h>
 
-enum ldo_reg {
-	LDO_ARM,
-	LDO_SOC,
-	LDO_PU,
-};
-
 struct scu_regs {
 	u32	ctrl;
 	u32	config;
@@ -255,7 +249,7 @@ static void clear_ldo_ramp(void)
  * Possible values are from 0.725V to 1.450V in steps of
  * 0.025V (25mV).
  */
-static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
+int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	u32 val, step, old, reg = readl(&anatop->reg_core);
@@ -375,6 +369,37 @@ static void init_bandgap(void)
 	}
 }
 
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+static void noc_setup(void)
+{
+	enable_ipu_clock();
+
+	writel(0x80000201, 0xbb0608);
+	/* Bypass IPU1 QoS generator */
+	writel(0x00000002, 0x00bb048c);
+	/* Bypass IPU2 QoS generator */
+	writel(0x00000002, 0x00bb050c);
+	/* Bandwidth THR for of PRE0 */
+	writel(0x00000200, 0x00bb0690);
+	/* Bandwidth THR for of PRE1 */
+	writel(0x00000200, 0x00bb0710);
+	/* Bandwidth THR for of PRE2 */
+	writel(0x00000200, 0x00bb0790);
+	/* Bandwidth THR for of PRE3 */
+	writel(0x00000200, 0x00bb0810);
+	/* Saturation THR for of PRE0 */
+	writel(0x00000010, 0x00bb0694);
+	/* Saturation THR for of PRE1 */
+	writel(0x00000010, 0x00bb0714);
+	/* Saturation THR for of PRE2 */
+	writel(0x00000010, 0x00bb0794);
+	/* Saturation THR for of PRE */
+	writel(0x00000010, 0x00bb0814);
+
+	disable_ipu_clock();
+}
+#endif
+
 int arch_cpu_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -452,6 +477,10 @@ int arch_cpu_init(void)
 
 	init_src();
 
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
+	if (is_mx6dqp())
+		noc_setup();
+#endif
 	return 0;
 }
 
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index ed5f0aeb2d..138c58363f 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -3,6 +3,11 @@ if ARCH_MX7ULP
 config SYS_SOC
 	default "mx7ulp"
 
+config LDO_ENABLED_MODE
+	bool "i.MX7ULP LDO Enabled Mode"
+	help
+	  Select this option to enable the PMC1 LDO.
+
 config MX7ULP
 	bool
 
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index 819c90af6c..c7bb7a1c66 100644
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -949,67 +949,6 @@ void scg_a7_ddrclk_init(void)
 /* Clock source is System OSC <<0 */
 #define SCG1_APLL_CFG_CLKSRC_NUM        ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
 
-/*
- * A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
- * system PLL is sourced from APLL,
- * APLL clock source is system OSC (24MHz)
- */
-#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM     |   \
-				   SCG1_APLL_CFG_POSTDIV1_NUM     |   \
-				   (22 << SCG_PLL_CFG_MULT_SHIFT) |   \
-				   SCG1_APLL_CFG_PFDSEL_NUM       |   \
-				   SCG1_APLL_CFG_PREDIV_NUM       |   \
-				   SCG1_APLL_CFG_BYPASS_NUM       |   \
-				   SCG1_APLL_CFG_PLLSEL_NUM       |   \
-				   SCG1_APLL_CFG_CLKSRC_NUM)
-
-/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
-#define SCG1_APLL_PFD0_FRAC_NUM (27)
-
-
-void scg_a7_apll_init(void)
-{
-	u32 val = 0;
-
-	/* Disable A7 Auxiliary PLL */
-	val = readl(&scg1_regs->apllcsr);
-	val &= ~SCG_APLL_CSR_APLLEN_MASK;
-	writel(val, &scg1_regs->apllcsr);
-
-	/* Gate off A7 APLL PFD0 ~ PDF4  */
-	val = readl(&scg1_regs->apllpfd);
-	val |= 0x80808080;
-	writel(val, &scg1_regs->apllpfd);
-
-	/* ================ A7 APLL Configuration Start ============== */
-	/* Configure A7 Auxiliary PLL */
-	writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
-
-	/* Enable A7 Auxiliary PLL */
-	val = readl(&scg1_regs->apllcsr);
-	val |= SCG_APLL_CSR_APLLEN_MASK;
-	writel(val, &scg1_regs->apllcsr);
-
-	/* Wait for A7 APLL clock ready */
-	while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
-		;
-
-	/* Configure A7 APLL PFD0 */
-	val = readl(&scg1_regs->apllpfd);
-	val &= ~SCG_PLL_PFD0_FRAC_MASK;
-	val |= SCG1_APLL_PFD0_FRAC_NUM;
-	writel(val, &scg1_regs->apllpfd);
-
-	/* Un-gate A7 APLL PFD0 */
-	val = readl(&scg1_regs->apllpfd);
-	val &= ~SCG_PLL_PFD0_GATE_MASK;
-	writel(val, &scg1_regs->apllpfd);
-
-	/* Wait for A7 APLL PFD0 clock being valid */
-	while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
-		;
-}
-
 /* SCG1(A7) FIRC DIV configurations */
 /* Disable FIRC DIV3 */
 #define SCG1_FIRCDIV_DIV3_NUM           ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 4b6014e724..8345b01398 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -10,6 +10,22 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/hab.h>
 
+#define PMC0_BASE_ADDR		0x410a1000
+#define PMC0_CTRL		0x28
+#define PMC0_CTRL_LDOEN		BIT(31)
+#define PMC0_CTRL_LDOOKDIS	BIT(30)
+#define PMC0_CTRL_PMC1ON	BIT(24)
+#define PMC1_BASE_ADDR		0x40400000
+#define PMC1_RUN		0x8
+#define PMC1_STOP		0x10
+#define PMC1_VLPS		0x14
+#define PMC1_LDOVL_SHIFT	16
+#define PMC1_LDOVL_MASK		(0x3f << PMC1_LDOVL_SHIFT)
+#define PMC1_LDOVL_900		0x1e
+#define PMC1_LDOVL_950		0x23
+#define PMC1_STATUS		0x20
+#define PMC1_STATUS_LDOVLF	BIT(8)
+
 static char *get_reset_cause(char *);
 
 #if defined(CONFIG_IMX_HAB)
@@ -101,6 +117,44 @@ void init_wdog(void)
 	disable_wdog(WDG2_RBASE);
 }
 
+#if defined(CONFIG_LDO_ENABLED_MODE)
+static void init_ldo_mode(void)
+{
+	unsigned int reg;
+
+	/* Set LDOOKDIS */
+	setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
+
+	/* Set LDOVL to 0.95V in PMC1_RUN */
+	reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
+	reg &= ~PMC1_LDOVL_MASK;
+	reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
+	writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
+
+	/* Wait for LDOVLF to be cleared */
+	reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
+	while (reg & PMC1_STATUS_LDOVLF)
+		;
+
+	/* Set LDOVL to 0.95V in PMC1_STOP */
+	reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
+	reg &= ~PMC1_LDOVL_MASK;
+	reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
+	writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
+
+	/* Set LDOVL to 0.90V in PMC1_VLPS */
+	reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
+	reg &= ~PMC1_LDOVL_MASK;
+	reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
+	writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
+
+	/* Set LDOEN bit */
+	setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
+
+	/* Set the PMC1ON bit */
+	setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
+}
+#endif
 
 void s_init(void)
 {
@@ -114,6 +168,10 @@ void s_init(void)
 		/* enable dumb pmic */
 		writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
 	}
+
+#if defined(CONFIG_LDO_ENABLED_MODE)
+	init_ldo_mode();
+#endif
 	return;
 }
 
@@ -132,6 +190,21 @@ const char *get_imx_type(u32 imxtype)
 	return "7ULP";
 }
 
+#define PMC0_BASE_ADDR		0x410a1000
+#define PMC0_CTRL		0x28
+#define PMC0_CTRL_LDOEN		BIT(31)
+
+static bool ldo_mode_is_enabled(void)
+{
+	unsigned int reg;
+
+	reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
+	if (reg & PMC0_CTRL_LDOEN)
+		return true;
+	else
+		return false;
+}
+
 int print_cpuinfo(void)
 {
 	u32 cpurev;
@@ -160,6 +233,11 @@ int print_cpuinfo(void)
 		break;
 	}
 
+	if (ldo_mode_is_enabled())
+		printf("PMC1:  LDO enabled mode\n");
+	else
+		printf("PMC1:  LDO bypass mode\n");
+
 	return 0;
 }
 #endif