diff options
author | Tom Rini <trini@konsulko.com> | 2019-10-14 13:00:51 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2019-10-14 13:00:51 -0400 |
commit | 6f1f28b8e19a0d48b930a577fd8c8579cb66079b (patch) | |
tree | 44cdc42f3ea248c68a042532daf875799563a758 /arch/arm/mach-imx | |
parent | cd5ffc5de5a26f5b785e25654977fee25779b3e4 (diff) | |
parent | d02be21d3004b51c6fc9a54b90d31dcc2dac4a9a (diff) |
Merge tag 'u-boot-imx-20191014' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20191014
-------------------
Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
- logicpd pinmux
- i.MX7ULP: imx_ddr_size
- fixes Toradex i.MX6/i.MX7
- pico-imx7d
- tpc70 converted to DM
- New Board: meerkat96
- add HAB version command
- i.MX8 :
imx8: Jump from alias to OCRAM address at SPL init
imx8qm/qxp: Set SPL TEXT base to OCRAM base
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/mach-imx/cpu.c | 53 | ||||
-rw-r--r-- | arch/arm/mach-imx/hab.c | 21 | ||||
-rw-r--r-- | arch/arm/mach-imx/mmdc_size.c | 57 | ||||
-rw-r--r-- | arch/arm/mach-imx/mx6/Kconfig | 10 | ||||
-rw-r--r-- | arch/arm/mach-imx/mx7/Kconfig | 10 |
6 files changed, 102 insertions, 54 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index fbd99a3499..9dfe883ead 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -21,6 +21,9 @@ endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) obj-y += cpu.o speed.o +ifneq ($(CONFIG_MX51),y) +obj-y += mmdc_size.o +endif obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif @@ -48,7 +51,7 @@ obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif ifeq ($(SOC),$(filter $(SOC),mx7ulp)) -obj-y += cache.o +obj-y += cache.o mmdc_size.o obj-$(CONFIG_IMX_HAB) += hab.o endif ifeq ($(SOC),$(filter $(SOC),vf610)) diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index efd8fc614a..d39f607e3f 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -87,59 +87,6 @@ static char *get_reset_cause(void) } #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) -#if defined(CONFIG_MX53) -#define MEMCTL_BASE ESDCTL_BASE_ADDR -#else -#define MEMCTL_BASE MMDC_P0_BASE_ADDR -#endif -static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; -static const unsigned char bank_lookup[] = {3, 2}; - -/* these MMDC registers are common to the IMX53 and IMX6 */ -struct esd_mmdc_regs { - uint32_t ctl; - uint32_t pdc; - uint32_t otc; - uint32_t cfg0; - uint32_t cfg1; - uint32_t cfg2; - uint32_t misc; -}; - -#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) -#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) -#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) -#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) -#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) - -/* - * imx_ddr_size - return size in bytes of DRAM according MMDC config - * The MMDC MDCTL register holds the number of bits for row, col, and data - * width and the MMDC MDMISC register holds the number of banks. Combine - * all these bits to determine the meme size the MMDC has been configured for - */ -unsigned imx_ddr_size(void) -{ - struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; - unsigned ctl = readl(&mem->ctl); - unsigned misc = readl(&mem->misc); - int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ - - bits += ESD_MMDC_CTL_GET_ROW(ctl); - bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; - bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; - bits += ESD_MMDC_CTL_GET_WIDTH(ctl); - bits += ESD_MMDC_CTL_GET_CS1(ctl); - - /* The MX6 can do only 3840 MiB of DRAM */ - if (bits == 32) - return 0xf0000000; - - return 1 << bits; -} -#endif - #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) const char *get_imx_type(u32 imxtype) diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index ce50dbe907..30db820b56 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -365,6 +365,21 @@ static int do_hab_failsafe(cmd_tbl_t *cmdtp, int flag, int argc, return 0; } +static int do_hab_version(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct hab_hdr *hdr = (struct hab_hdr *)HAB_RVT_BASE; + + if (hdr->tag != HAB_TAG_RVT) { + printf("Unexpected header tag: %x\n", hdr->tag); + return CMD_RET_FAILURE; + } + + printf("HAB version: %d.%d\n", hdr->par >> 4, hdr->par & 0xf); + + return 0; +} + static int do_authenticate_image_or_failover(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -421,6 +436,12 @@ U_BOOT_CMD( "ivt_offset - hex offset of IVT in the image" ); +U_BOOT_CMD( + hab_version, 1, 0, do_hab_version, + "print HAB major/minor version", + "" + ); + #endif /* !defined(CONFIG_SPL_BUILD) */ /* Get CSF Header length */ diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c new file mode 100644 index 0000000000..1a094726aa --- /dev/null +++ b/arch/arm/mach-imx/mmdc_size.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <asm/io.h> + +#if defined(CONFIG_MX53) +#define MEMCTL_BASE ESDCTL_BASE_ADDR +#elif defined(CONFIG_MX6) +#define MEMCTL_BASE MMDC_P0_BASE_ADDR +#elif defined(CONFIG_MX7ULP) +#define MEMCTL_BASE MMDC0_RBASE +#endif +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; +static const unsigned char bank_lookup[] = {3, 2}; + +/* these MMDC registers are common to the IMX53 and IMX6 */ +struct esd_mmdc_regs { + u32 ctl; + u32 pdc; + u32 otc; + u32 cfg0; + u32 cfg1; + u32 cfg2; + u32 misc; +}; + +#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) +#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) +#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) +#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) +#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) + +/* + * imx_ddr_size - return size in bytes of DRAM according MMDC config + * The MMDC MDCTL register holds the number of bits for row, col, and data + * width and the MMDC MDMISC register holds the number of banks. Combine + * all these bits to determine the meme size the MMDC has been configured for + */ +unsigned int imx_ddr_size(void) +{ + struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; + unsigned int ctl = readl(&mem->ctl); + unsigned int misc = readl(&mem->misc); + int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ + + bits += ESD_MMDC_CTL_GET_ROW(ctl); + bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; + bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; + bits += ESD_MMDC_CTL_GET_WIDTH(ctl); + bits += ESD_MMDC_CTL_GET_CS1(ctl); + + /* The MX6 can do only 3840 MiB of DRAM */ + if (bits == 32) + return 0xf0000000; + + return 1 << bits; +} diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7e5a667e81..00e3c486bc 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -510,9 +510,19 @@ config TARGET_KP_IMX6Q_TPC select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM + select SPL_DM if SPL select DM_THERMAL + select DM_MMC + select DM_ETH + select DM_REGULATOR + select SPL_DM_REGULATOR if SPL + select DM_SERIAL + select DM_I2C + select DM_GPIO + select DM_USB select MX6QDL select SUPPORT_SPL + select SPL_SEPARATE_BSS if SPL imply CMD_DM imply CMD_SPL diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 232f33285d..286d36589d 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -28,6 +28,15 @@ config TARGET_CL_SOM_IMX7 select SUPPORT_SPL imply CMD_DM +config TARGET_MEERKAT96 + bool "NovTech Meerkat96 board" + select BOARD_LATE_INIT + select DM + select DM_SERIAL + select DM_THERMAL + select MX7D + imply CMD_DM + config TARGET_MX7DSABRESD bool "mx7dsabresd" select BOARD_LATE_INIT @@ -67,6 +76,7 @@ config SYS_SOC source "board/compulab/cl-som-imx7/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" +source "board/novtech/meerkat96/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" |