diff options
| author | Bai Ping <ping.bai@nxp.com> | 2019-07-22 01:24:42 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-10-08 16:35:16 +0200 |
| commit | 7777406a8a023bdfe18d106138c61eeaa15dd5b4 (patch) | |
| tree | 29fe1e3eb968ea0130d44b023951e25ae0306c79 /arch/arm/mach-imx | |
| parent | bd1cc6ae6f8a8f2c1c44263e3a89f853c237306e (diff) | |
i.MX7ULP: Fix system reset after a7 rtc alarm expired.
The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access
it. So check the CPU rev and not apply the settings for B0.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp/soc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 6015c11869..7119ee4a07 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -106,6 +106,10 @@ void s_init(void) /* clock configuration. */ clock_init(); + if (soc_rev() < CHIP_REV_2_0) { + /* enable dumb pmic */ + writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR); + } return; } |