arm: Add support for Qualcomm IPQ40xx family

This introduces initial support for the popular Qualcomm
IPQ40x8 and IPQ40x9 WiSoC series.

IPQ40xx series have 4x Cortex A7 ARM-v7A cores.
Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029.

IPQ40x8 and IPQ40x9 use the same cores, but differ in
addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8)
and supported peripherals (IPQ40x8 lacks RGMII, LCD controller
and EMMC/SDHCI controllers).

IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only
by their rated temperatures rates with IPQ402X models being
rated for wider temperature ranges.

Initially this supports:
* Simple clock driver (Only for UART1 now, will be extended)
* Pinctrl driver (Supports UARTX and GPIO now, will be extended)
* GPIOs already supported by msm_gpio driver with updates
* UARTs already supported by serial_msm driver with updates

Further peripherals will come in later patches.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>

1 files changed, 64 insertions, 0 deletions

diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c
new file mode 100644
index 0000000000..7cf98a203c
--- /dev/null
+++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock drivers for Qualcomm IPQ40xx
+ *
+ * Copyright (c) 2019 Sartura Ltd.
+ *
+ * Author: Robert Marko <robert.marko@sartura.hr>
+ *
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+
+struct msm_clk_priv {
+	phys_addr_t base;
+};
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+	switch (clk->id) {
+	case 26: /*UART1*/
+		/* This clock is already initialized by SBL1 */
+		return 0; 
+		break;
+	default:
+		return 0;
+	}
+}
+
+static int msm_clk_probe(struct udevice *dev)
+{
+	struct msm_clk_priv *priv = dev_get_priv(dev);
+
+	priv->base = devfdt_get_addr(dev);
+	if (priv->base == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	return 0;
+}
+
+static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
+{
+	return msm_set_rate(clk, rate);
+}
+
+static struct clk_ops msm_clk_ops = {
+	.set_rate = msm_clk_set_rate,
+};
+
+static const struct udevice_id msm_clk_ids[] = {
+	{ .compatible = "qcom,gcc-ipq4019" },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_msm) = {
+	.name		= "clk_msm",
+	.id		= UCLASS_CLK,
+	.of_match	= msm_clk_ids,
+	.ops		= &msm_clk_ops,
+	.priv_auto_alloc_size = sizeof(struct msm_clk_priv),
+	.probe		= msm_clk_probe,
+};