arm: mach-k3: Enable WA for R5F deadlock

On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
  cacheable write back/write allocate memory region and later
  on software execute barrier operation (DSB or DMB). R5F may
  hang at the barrier instruction.
2.When software is performing a mix of load and store operations
  within a tight loop and store operations are all writing to
  cacheable write back/write allocates memory regions, R5F may
  hang at one of the load instruction.

To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

1 files changed, 25 insertions, 0 deletions

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index bf631b74f8..50f5b81dfe 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -244,3 +244,28 @@ void board_prep_linux(bootm_headers_t *images)
 				       CONFIG_SYS_CACHELINE_SIZE));
 }
 #endif
+
+#ifdef CONFIG_CPU_V7R
+void disable_linefill_optimization(void)
+{
+	u32 actlr;
+
+	/*
+	 * On K3 devices there are 2 conditions where R5F can deadlock:
+	 * 1.When software is performing series of store operations to
+	 *   cacheable write back/write allocate memory region and later
+	 *   on software execute barrier operation (DSB or DMB). R5F may
+	 *   hang at the barrier instruction.
+	 * 2.When software is performing a mix of load and store operations
+	 *   within a tight loop and store operations are all writing to
+	 *   cacheable write back/write allocates memory regions, R5F may
+	 *   hang at one of the load instruction.
+	 *
+	 * To avoid the above two conditions disable linefill optimization
+	 * inside Cortex R5F.
+	 */
+	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
+	actlr |= (1 << 13); /* Set DLFO bit  */
+	asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
+}
+#endif