diff options
author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-06-13 10:29:43 +0530 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2019-07-26 21:49:26 -0400 |
commit | 0a704924f3725cbf1dffe88f94252a22ccc7af12 (patch) | |
tree | 0a43c5295f91baec4dc21d13f29e3a518c1c3fad /arch/arm/mach-k3/include/mach | |
parent | c2562d7c9e50e2e8afbda4aa0f13698a1a16de06 (diff) |
armv7R: K3: j721e: Add support for boot device detection
J721E allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Diffstat (limited to 'arch/arm/mach-k3/include/mach')
-rw-r--r-- | arch/arm/mach-k3/include/mach/hardware.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/j721e_hardware.h | 49 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/j721e_spl.h | 31 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/spl.h | 4 |
4 files changed, 88 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index b39f780d26..4e629822aa 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -9,4 +9,8 @@ #ifdef CONFIG_SOC_K3_AM6 #include "am6_hardware.h" #endif + +#ifdef CONFIG_SOC_K3_J721E +#include "j721e_hardware.h" +#endif #endif /* _ASM_ARCH_HARDWARE_H_ */ diff --git a/arch/arm/mach-k3/include/mach/j721e_hardware.h b/arch/arm/mach-k3/include/mach/j721e_hardware.h new file mode 100644 index 0000000000..8d429772b5 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j721e_hardware.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: J721E SoC definitions, structures etc. + * + * (C) Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef __ASM_ARCH_J721E_HARDWARE_H +#define __ASM_ARCH_J721E_HARDWARE_H + +#include <config.h> + +#define CTRL_MMR0_BASE 0x00100000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) + +#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) +#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 +#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) +#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6) +#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6 + +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 + +#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) +#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism + * shared register definitions. + */ +#define CTRLMMR_LOCK_KICK0 0x01008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) +#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 +#define CTRLMMR_LOCK_KICK1 0x0100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +#endif /* __ASM_ARCH_J721E_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h new file mode 100644 index 0000000000..2b52faf944 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j721e_spl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ +#ifndef _ASM_ARCH_J721E_SPL_H_ +#define _ASM_ARCH_J721E_SPL_H_ + +/* With BootMode B = 0 */ +#define BOOT_DEVICE_HYPERFLASH 0x00 +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 + +/* With BootMode B = 1 */ +#define BOOT_DEVICE_MMC2 0x10 +#define BOOT_DEVICE_MMC1 0x11 +#define BOOT_DEVICE_USB 0x12 +#define BOOT_DEVICE_UFS 0x13 +#define BOOT_DEVIE_GPMC 0x14 +#define BOOT_DEVICE_PCIE 0x15 +#define BOOT_DEVICE_MMC2_2 0x16 +#define BOOT_DEVICE_RAM 0x17 + +#define BOOT_MODE_B_SHIFT 4 +#define BOOT_MODE_B_MASK BIT(4) + +#endif diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index 2d435aec17..a26c8ecdd5 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -9,4 +9,8 @@ #ifdef CONFIG_SOC_K3_AM6 #include "am6_spl.h" #endif + +#ifdef CONFIG_SOC_K3_J721E +#include "j721e_spl.h" +#endif #endif /* _ASM_ARCH_SPL_H_ */ |