diff options
| author | Lokesh Vutla <lokeshvutla@ti.com> | 2018-11-15 11:04:50 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-11-26 22:52:11 -0500 |
| commit | ccdb7c2255bde555bd0d4e104f8d228e25b76572 (patch) | |
| tree | 0729f8f35361062cc31ec767dc5f7852c63a6396 /arch/arm/mach-k3/lowlevel_init.S | |
| parent | f7bb20a53e829ce0b4d3c22c704e80b490d24016 (diff) | |
armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.
If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.
If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-k3/lowlevel_init.S')
| -rw-r--r-- | arch/arm/mach-k3/lowlevel_init.S | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/lowlevel_init.S b/arch/arm/mach-k3/lowlevel_init.S new file mode 100644 index 0000000000..70c5d1cade --- /dev/null +++ b/arch/arm/mach-k3/lowlevel_init.S @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Lokesh Vutla <lokeshvutla@ti.com> + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + + mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR + and r0, #0xff + cmp r0, #0x0 + bne park_cpu + bx lr +park_cpu: + wfi + b park_cpu + +ENDPROC(lowlevel_init) |