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authorLokesh Vutla <lokeshvutla@ti.com>2015-07-28 14:16:44 +0530
committerTom Rini <trini@konsulko.com>2015-08-12 20:47:52 -0400
commit7b50e1599f4e6551a3348ca5f061a596f6f6896e (patch)
tree5377f6c888f9f71cb4e8eb6f58de36d1cf41471d /arch/arm/mach-keystone/include/mach/clock-k2l.h
parentc321a2362463ce54ae73ef59bee4b620d9f26acf (diff)
ARM: keystone2: Fix dev and arm speed detection
Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/include/mach/clock-k2l.h')
-rw-r--r--arch/arm/mach-keystone/include/mach/clock-k2l.h14
1 files changed, 5 insertions, 9 deletions
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2l.h b/arch/arm/mach-keystone/include/mach/clock-k2l.h
index bb9a5c4dcf..c145a1eeb0 100644
--- a/arch/arm/mach-keystone/include/mach/clock-k2l.h
+++ b/arch/arm/mach-keystone/include/mach/clock-k2l.h
@@ -59,15 +59,6 @@ enum pll_type_e {
DDR3_PLL,
};
-enum {
- SPD800,
- SPD1000,
- SPD1200,
- SPD1350,
- SPD1400,
- SPD_RSV
-};
-
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
@@ -92,4 +83,9 @@ enum {
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
+/* k2l DEV supports 800, 1000, 1200 MHz */
+#define DEV_SUPPORTED_SPEEDS 0x383
+/* k2l ARM supportd 800, 1000, 1200, MHz */
+#define ARM_SUPPORTED_SPEEDS 0x383
+
#endif