diff options
| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-02-20 17:04:18 +0900 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-02-21 08:23:52 -0500 |
| commit | dc7de222aa82cc962f15b5d04e1e4c6b0ab62398 (patch) | |
| tree | 31443e719f54f025300e213138db5e86ea35b216 /arch/arm/mach-keystone/include/mach/hardware-k2e.h | |
| parent | fd697ecf5d1797180c29328b013d48ee3a788e03 (diff) | |
ARM: keystone: move SoC headers to mach-keystone/include/mach
Move arch/arm/include/asm/arch-keystone/*
-> arch/arm/mach-keystone/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/mach-keystone/include/mach/hardware-k2e.h')
| -rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware-k2e.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2e.h b/arch/arm/mach-keystone/include/mach/hardware-k2e.h new file mode 100644 index 0000000000..df499957e5 --- /dev/null +++ b/arch/arm/mach-keystone/include/mach/hardware-k2e.h @@ -0,0 +1,65 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 13 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02324000 +#define KS2_LANES_PER_SGMII_SERDES 4 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 +#define KS2_NETCP_PDMA_TX_BASE 0x24187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x24188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 + +/* NETCP */ +#define KS2_NETCP_BASE 0x24000000 + +#endif |