diff options
| author | Nishanth Menon <nm@ti.com> | 2016-03-23 10:14:19 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-04-01 17:17:40 -0400 |
| commit | 2283284b05326bf1384873f2a59b77fe0d9b2f8f (patch) | |
| tree | de8dee4a8c1c0475b6c61e920fbb7a14eb0f781d /arch/arm/mach-keystone/include/mach | |
| parent | 1f807a9f32aaa4e4917336912fd867671954d18c (diff) | |
ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.
Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)
Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K | K2L | K2E | K2G
-------+-----------+-----------+-----------+---------
0 | C66x 0 | C66x 0 | C66x 0 | C66x 0
1 | C66x 1 | C66x 1 | Reserved | ARM
2 | C66x 2 | C66x 2 | Reserved | ICSS0
3 | C66x 3 | C66x 3 | Reserved | ICSS1
4 | C66x 4 | Reserved | Reserved | NETCP
5 | C66x 5 | Reserved | Reserved | CPIE
6 | C66x 6 | Reserved | Reserved | USB
7 | C66x 7 | Reserved | Reserved | Reserved
8 | ARM | ARM | ARM | MLB
9 | NetCP | NetCP | NetCP | PMMC
10 | QM_PDSP | QM_PDSP | QM_PDSP | DSS
11 | PCIe_0 | PCIe_0 | PCIe_0 | MMC
12 | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13 | Reserved | Reserved | PCIe_1 | Reserved
14 | HyperLink | PCIe_1 | HyperLink | Reserved
15 | Reserved | Reserved | TSIP | Reserved
-------+-----------+-----------+-----------+---------
NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.
Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).
By marking these segments as shared, we also ensure SoC wide coherency
is enabled.
Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-keystone/include/mach')
| -rw-r--r-- | arch/arm/mach-keystone/include/mach/hardware.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h index dd9268fbf2..38d019056a 100644 --- a/arch/arm/mach-keystone/include/mach/hardware.h +++ b/arch/arm/mach-keystone/include/mach/hardware.h @@ -216,22 +216,45 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_MSMC_CTRL_BASE 0x0bc00000 #define KS2_MSMC_DATA_BASE 0x0c000000 +/* KS2 Generic Privilege ID Settings for MSMC2 */ +#define KS2_MSMC_SEGMENT_C6X_0 0 +#define KS2_MSMC_SEGMENT_C6X_1 1 +#define KS2_MSMC_SEGMENT_C6X_2 2 +#define KS2_MSMC_SEGMENT_C6X_3 3 +#define KS2_MSMC_SEGMENT_C6X_4 4 +#define KS2_MSMC_SEGMENT_C6X_5 5 +#define KS2_MSMC_SEGMENT_C6X_6 6 +#define KS2_MSMC_SEGMENT_C6X_7 7 + +#define KS2_MSMC_SEGMENT_DEBUG 12 + /* KS2 HK/L/E MSMC PRIVIDs for MSMC2 */ #define K2HKLE_MSMC_SEGMENT_ARM 8 #define K2HKLE_MSMC_SEGMENT_NETCP 9 #define K2HKLE_MSMC_SEGMENT_QM_PDSP 10 #define K2HKLE_MSMC_SEGMENT_PCIE0 11 +/* K2HK specific Privilege ID Settings */ +#define K2HKE_MSMC_SEGMENT_HYPERLINK 14 + /* K2L specific Privilege ID Settings */ #define K2L_MSMC_SEGMENT_PCIE1 14 /* K2E specific Privilege ID Settings */ #define K2E_MSMC_SEGMENT_PCIE1 13 +#define K2E_MSMC_SEGMENT_TSIP 15 /* K2G specific Privilege ID Settings */ #define K2G_MSMC_SEGMENT_ARM 1 +#define K2G_MSMC_SEGMENT_ICSS0 2 +#define K2G_MSMC_SEGMENT_ICSS1 3 #define K2G_MSMC_SEGMENT_NSS 4 #define K2G_MSMC_SEGMENT_PCIE 5 +#define K2G_MSMC_SEGMENT_USB 6 +#define K2G_MSMC_SEGMENT_MLB 8 +#define K2G_MSMC_SEGMENT_PMMC 9 +#define K2G_MSMC_SEGMENT_DSS 10 +#define K2G_MSMC_SEGMENT_MMC 11 /* MSMC segment size shift bits */ #define KS2_MSMC_SEG_SIZE_SHIFT 12 |