Merge branch 'master' of git://git.denx.de/u-boot

12 files changed, 277 insertions, 8 deletions

diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 67f1a33241..e1962c779a 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -13,6 +13,9 @@ config TARGET_K2E_EVM
 config TARGET_K2L_EVM
 	bool "TI Keystone 2 Lamar EVM"
 
+config TARGET_K2G_EVM
+	bool "TI Keystone 2 Galileo EVM"
+
 endchoice
 
 config SYS_SOC
diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c
index fc3eadb3f2..5c6051e76d 100644
--- a/arch/arm/mach-keystone/clock.c
+++ b/arch/arm/mach-keystone/clock.c
@@ -31,8 +31,14 @@ const struct keystone_pll_regs keystone_pll_regs[] = {
 	[TETRIS_PLL]	= {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
 	[DDR3A_PLL]	= {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
 	[DDR3B_PLL]	= {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
+	[UART_PLL]	= {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
 };
 
+inline void pll_pa_clk_sel(void)
+{
+	setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
+}
+
 static void wait_for_completion(const struct pll_init_data *data)
 {
 	int i;
@@ -180,9 +186,8 @@ void configure_secondary_pll(const struct pll_init_data *data)
 	sdelay(21000);
 
 	/* Select the Output of PASS PLL as input to PASS */
-	if (data->pll == PASS_PLL)
-		setbits_le32(keystone_pll_regs[data->pll].reg1,
-			     CFG_PLLCTL1_PAPLL_MASK);
+	if (data->pll == PASS_PLL && cpu_is_k2hk())
+		pll_pa_clk_sel();
 
 	/* Select the Output of ARM PLL as input to ARM */
 	if (data->pll == TETRIS_PLL)
@@ -309,6 +314,10 @@ static unsigned long pll_freq_get(int pll)
 			ret = external_clk[ddr3b_clk];
 			reg = KS2_DDR3BPLLCTL0;
 			break;
+		case UART_PLL:
+			ret = external_clk[uart_clk];
+			reg = KS2_UARTPLLCTL0;
+			break;
 		default:
 			return 0;
 		}
@@ -351,6 +360,10 @@ unsigned long clk_get_rate(unsigned int clk)
 		if (cpu_is_k2hk())
 			freq = pll_freq_get(DDR3B_PLL);
 		break;
+	case uart_pll_clk:
+		if (cpu_is_k2g())
+			freq = pll_freq_get(UART_PLL);
+		break;
 	case sys_clk0_1_clk:
 	case sys_clk0_clk:
 		freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
diff --git a/arch/arm/mach-keystone/cmd_mon.c b/arch/arm/mach-keystone/cmd_mon.c
index 73ceb83072..a539d5d275 100644
--- a/arch/arm/mach-keystone/cmd_mon.c
+++ b/arch/arm/mach-keystone/cmd_mon.c
@@ -37,7 +37,7 @@ static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc,
 	if (argc < 2)
 		return CMD_RET_USAGE;
 
-	freq = clk_get_rate(sys_clk0_6_clk);
+	freq = CONFIG_SYS_HZ_CLOCK;
 
 	addr = simple_strtoul(argv[1], NULL, 16);
 
diff --git a/arch/arm/mach-keystone/config.mk b/arch/arm/mach-keystone/config.mk
index ceacffa8af..9ae1e9ac91 100644
--- a/arch/arm/mach-keystone/config.mk
+++ b/arch/arm/mach-keystone/config.mk
@@ -16,13 +16,13 @@ spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE
 
 OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
 			  --gap-fill=0
-u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
+u-boot-spi.gph: spl/u-boot-spl.gph u-boot-dtb.img FORCE
 	$(call if_changed,pad_cat)
 
 ifndef CONFIG_SPL_BUILD
 MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \
 	-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -n U-Boot
-MLO: u-boot.bin FORCE
+MLO: u-boot-dtb.bin FORCE
 	$(call if_changed,mkimage)
 	@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
 endif
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index dfb27b5ba2..34606f4b2f 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -52,7 +52,8 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 	__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
 	__raw_writel(phy_cfg->mr0,   base + KS2_DDRPHY_MR0_OFFSET);
 	__raw_writel(phy_cfg->mr1,   base + KS2_DDRPHY_MR1_OFFSET);
-	__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
+	if (!cpu_is_k2g())
+		__raw_writel(phy_cfg->mr2,   base + KS2_DDRPHY_MR2_OFFSET);
 	__raw_writel(phy_cfg->dtcr,  base + KS2_DDRPHY_DTCR_OFFSET);
 	__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
 
@@ -64,6 +65,15 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
 		;
 
+	/* Disable ECC for K2G */
+	if (cpu_is_k2g()) {
+		clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
+		clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+	}
+
 	__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
 	while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
 		;
diff --git a/arch/arm/mach-keystone/include/mach/clock-k2g.h b/arch/arm/mach-keystone/include/mach/clock-k2g.h
new file mode 100644
index 0000000000..214c1d3a83
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/clock-k2g.h
@@ -0,0 +1,20 @@
+/*
+ * K2G: Clock data
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2G_H
+#define __ASM_ARCH_CLOCK_K2G_H
+
+#define PLLSET_CMD_LIST		"<pa|arm|ddr3>"
+
+#define DEV_SUPPORTED_SPEEDS	0xfff
+#define ARM_SUPPORTED_SPEEDS	0xfff
+
+#define KS2_CLK1_6 sys_clk0_6_clk
+
+#endif
diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h
index ddc5f8e501..cdcff3baee 100644
--- a/arch/arm/mach-keystone/include/mach/clock.h
+++ b/arch/arm/mach-keystone/include/mach/clock.h
@@ -24,8 +24,13 @@
 #include <asm/arch/clock-k2l.h>
 #endif
 
+#ifdef CONFIG_SOC_K2G
+#include <asm/arch/clock-k2g.h>
+#endif
+
 #define CORE_PLL MAIN_PLL
 #define DDR3_PLL DDR3A_PLL
+#define NSS_PLL PASS_PLL
 
 #define CLK_LIST(CLK)\
 	CLK(0, core_pll_clk)\
@@ -48,7 +53,8 @@
 	CLK(17, sys_clk1_6_clk)\
 	CLK(18, sys_clk1_12_clk)\
 	CLK(19, sys_clk2_clk)\
-	CLK(20, sys_clk3_clk)
+	CLK(20, sys_clk3_clk)\
+	CLK(21, uart_pll_clk)
 
 #include <asm/types.h>
 
@@ -75,6 +81,7 @@ enum {
 	PASS_PLL,
 	DDR3A_PLL,
 	DDR3B_PLL,
+	UART_PLL,
 	MAX_PLL_COUNT,
 };
 
@@ -85,6 +92,7 @@ enum ext_clk_e {
 	tetris_clk,
 	ddr3a_clk,
 	ddr3b_clk,
+	uart_clk,
 	ext_clk_count /* number of external clocks */
 };
 
@@ -118,6 +126,7 @@ unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 int clk_set_rate(unsigned int clk, unsigned long hz);
 int get_max_dev_speed(void);
 int get_max_arm_speed(void);
+void pll_pa_clk_sel(void);
 
 #endif
 #endif
diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
new file mode 100644
index 0000000000..fa4162fe99
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -0,0 +1,74 @@
+/*
+ * K2G: SoC definitions
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_K2G_H
+#define __ASM_ARCH_HARDWARE_K2G_H
+
+#define KS2_NUM_DSPS	0
+
+/* Power and Sleep Controller (PSC) Domains */
+#define KS2_LPSC_ALWAYSON		0
+#define KS2_LPSC_PMMC			1
+#define KS2_LPSC_DEBUG			2
+#define KS2_LPSC_NSS			3
+#define KS2_LPSC_SA			4
+#define KS2_LPSC_TERANET		5
+#define KS2_LPSC_SYS_COMP		6
+#define KS2_LPSC_QSPI			7
+#define KS2_LPSC_MMC			8
+#define KS2_LPSC_GPMC			9
+#define KS2_LPSC_MLB			11
+#define KS2_LPSC_EHRPWM			12
+#define KS2_LPSC_EQEP			13
+#define KS2_LPSC_ECAP			14
+#define KS2_LPSC_MCASP			15
+#define KS2_LPSC_SR			16
+#define KS2_LPSC_MSMC			17
+#define KS2_LPSC_GEM			18
+#define KS2_LPSC_ARM			19
+#define KS2_LPSC_ASRC			20
+#define KS2_LPSC_ICSS			21
+#define KS2_LPSC_DSS			23
+#define KS2_LPSC_PCIE			24
+#define KS2_LPSC_USB_0			25
+#define KS2_LPSC_USB			KS2_LPSC_USB_0
+#define KS2_LPSC_USB_1			26
+#define KS2_LPSC_DDR3			27
+#define KS2_LPSC_SPARE0_LPSC0		28
+#define KS2_LPSC_SPARE0_LPSC1		29
+#define KS2_LPSC_SPARE1_LPSC0		30
+#define KS2_LPSC_SPARE1_LPSC1		31
+
+#define KS2_LPSC_CPGMAC			KS2_LPSC_NSS
+#define KS2_LPSC_CRYPTO			KS2_LPSC_SA
+
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES	4
+
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE	0x04010000
+#define KS2_NETCP_PDMA_TX_BASE		0x04011000
+#define KS2_NETCP_PDMA_TX_CH_NUM	21
+#define KS2_NETCP_PDMA_RX_BASE		0x04012000
+#define KS2_NETCP_PDMA_RX_CH_NUM	32
+#define KS2_NETCP_PDMA_SCHED_BASE	0x04010100
+#define KS2_NETCP_PDMA_RX_FLOW_BASE	0x04013000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM	32
+#define KS2_NETCP_PDMA_TX_SND_QUEUE	5
+
+/* NETCP */
+#define KS2_NETCP_BASE			0x04000000
+
+#define K2G_GPIO0_BASE			0X02603000
+#define K2G_GPIO1_BASE			0X0260a000
+#define K2G_GPIO1_BANK2_BASE		K2G_GPIO1_BASE + 0x38
+#define K2G_GPIO_DIR_OFFSET		0x0
+#define K2G_GPIO_SETDATA_OFFSET		0x8
+
+#endif /* __ASM_ARCH_HARDWARE_K2G_H */
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index f98a24eb57..edebcd7bc5 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -52,6 +52,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
 #define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
 
+#define KS2_DDRPHY_DATX8_4_OFFSET       0x2C0
+#define KS2_DDRPHY_DATX8_5_OFFSET       0x300
+#define KS2_DDRPHY_DATX8_6_OFFSET       0x340
+#define KS2_DDRPHY_DATX8_7_OFFSET       0x380
 #define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
 
 #define IODDRM_MASK                     0x00000180
@@ -121,8 +125,13 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
 
 /* NETCP pktdma */
+#ifdef CONFIG_SOC_K2G
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE	113
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE	114
+#else
 #define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
+#endif
 
 /* Chip Interrupt Controller */
 #define KS2_CIC2_BASE			0x02608000
@@ -143,6 +152,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
 #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
 #define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
+#define KS2_ETHERNET_CFG		(KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
+#define KS2_ETHERNET_RGMII		2
 
 /* PSC */
 #define KS2_PSC_BASE			0x02350000
@@ -167,6 +178,8 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
 #define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
 #define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+#define KS2_UARTPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x390)
+#define KS2_UARTPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x394)
 
 #define KS2_PLL_CNTRL_BASE		0x02310000
 #define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
@@ -179,10 +192,17 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_RSTYPE_PLL_SOFT		BIT(13)
 
 /* SPI */
+#ifdef CONFIG_SOC_K2G
+#define KS2_SPI0_BASE			0x21805400
+#define KS2_SPI1_BASE			0x21805800
+#define KS2_SPI2_BASE			0x21805c00
+#define KS2_SPI3_BASE			0x21806000
+#else
 #define KS2_SPI0_BASE			0x21000400
 #define KS2_SPI1_BASE			0x21000600
 #define KS2_SPI2_BASE			0x21000800
 #define KS2_SPI_BASE			KS2_SPI0_BASE
+#endif
 
 /* AEMIF */
 #define KS2_AEMIF_CNTRL_BASE       	0x21000a00
@@ -194,10 +214,16 @@ typedef volatile unsigned int   *dv_reg_p;
 /* MSMC control */
 #define KS2_MSMC_CTRL_BASE		0x0bc00000
 #define KS2_MSMC_DATA_BASE		0x0c000000
+#ifndef CONFIG_SOC_K2G
 #define KS2_MSMC_SEGMENT_TETRIS		8
 #define KS2_MSMC_SEGMENT_NETCP		9
 #define KS2_MSMC_SEGMENT_QM_PDSP	10
 #define KS2_MSMC_SEGMENT_PCIE0		11
+#else
+#define KS2_MSMC_SEGMENT_TETRIS		1
+#define KS2_MSMC_SEGMENT_NETCP		4
+#define KS2_MSMC_SEGMENT_PCIE0		5
+#endif
 
 /* MSMC segment size shift bits */
 #define KS2_MSMC_SEG_SIZE_SHIFT		12
@@ -211,6 +237,22 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
 
 /* Queue manager */
+#ifdef CONFIG_SOC_K2G
+#define KS2_QM_BASE_ADDRESS		0x040C0000
+#define KS2_QM_CONF_BASE		0x04040000
+#define KS2_QM_DESC_SETUP_BASE		0x04080000
+#define KS2_QM_STATUS_RAM_BASE		0x0 /* K2G doesn't have it */
+#define KS2_QM_INTD_CONF_BASE		0x0
+#define KS2_QM_PDSP1_CMD_BASE		0x0
+#define KS2_QM_PDSP1_CTRL_BASE		0x0
+#define KS2_QM_PDSP1_IRAM_BASE		0x0
+#define KS2_QM_MANAGER_QUEUES_BASE	0x040c0000
+#define KS2_QM_MANAGER_Q_PROXY_BASE	0x04040200
+#define KS2_QM_QUEUE_STATUS_BASE	0x04100000
+#define KS2_QM_LINK_RAM_BASE		0x04020000
+#define KS2_QM_REGION_NUM		8
+#define KS2_QM_QPOOL_NUM		112
+#else
 #define KS2_QM_BASE_ADDRESS		0x23a80000
 #define KS2_QM_CONF_BASE		0x02a02000
 #define KS2_QM_DESC_SETUP_BASE		0x02a03000
@@ -225,6 +267,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define KS2_QM_LINK_RAM_BASE		0x00100000
 #define KS2_QM_REGION_NUM		64
 #define KS2_QM_QPOOL_NUM		4000
+#endif
 
 /* USB */
 #define KS2_USB_SS_BASE			0x02680000
@@ -247,6 +290,7 @@ typedef volatile unsigned int   *dv_reg_p;
 #define CPU_66AK2Hx	0xb981
 #define CPU_66AK2Ex	0xb9a6
 #define CPU_66AK2Lx	0xb9a7
+#define CPU_66AK2Gx	0xbb06
 
 /* DEVSPEED register */
 #define DEVSPEED_DEVSPEED_SHIFT	16
@@ -267,6 +311,10 @@ typedef volatile unsigned int   *dv_reg_p;
 #include <asm/arch/hardware-k2l.h>
 #endif
 
+#ifdef CONFIG_SOC_K2G
+#include <asm/arch/hardware-k2g.h>
+#endif
+
 #ifndef __ASSEMBLY__
 
 static inline u16 get_part_number(void)
@@ -291,6 +339,11 @@ static inline u8 cpu_is_k2l(void)
 	return get_part_number() == CPU_66AK2Lx;
 }
 
+static inline u8 cpu_is_k2g(void)
+{
+	return get_part_number() == CPU_66AK2Gx;
+}
+
 static inline u8 cpu_revision(void)
 {
 	u32 jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
diff --git a/arch/arm/mach-keystone/include/mach/mmc_host_def.h b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
new file mode 100644
index 0000000000..a5050ac0f1
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/mmc_host_def.h
@@ -0,0 +1,22 @@
+/*
+ * K2G: MMC
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef K2G_MMC_HOST_DEF_H
+#define K2G_MMC_HOST_DEF_H
+
+#include <asm/omap_mmc.h>
+
+/*
+ * OMAP HSMMC register definitions
+ */
+
+#define OMAP_HSMMC1_BASE	0x23000100
+#define OMAP_HSMMC2_BASE	0x23100100
+
+#endif /* K2G_MMC_HOST_DEF_H */
diff --git a/arch/arm/mach-keystone/include/mach/mux-k2g.h b/arch/arm/mach-keystone/include/mach/mux-k2g.h
new file mode 100644
index 0000000000..6167d2c338
--- /dev/null
+++ b/arch/arm/mach-keystone/include/mach/mux-k2g.h
@@ -0,0 +1,58 @@
+/*
+ * K2G: Pinmux configuration
+ *
+ * (C) Copyright 2015
+ *     Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MUX_K2G_H
+#define __ASM_ARCH_MUX_K2G_H
+
+#include <common.h>
+#include <asm/io.h>
+
+#define K2G_PADCFG_REG	(KS2_DEVICE_STATE_CTRL_BASE + 0x1000)
+
+/*
+ * 20:19 - buffer class RW fixed
+ * 18    - rxactive (Input enabled for the pad ) 0 - Di; 1 - En;
+ * 17    - pulltypesel (0 - PULLDOWN; 1 - PULLUP);
+ * 16    - pulluden (0 - PULLUP/DOWN EN; 1 - DI);
+ * 3:0   - muxmode (available modes 0:5)
+ */
+
+#define PIN_IEN	(1 << 18) /* pin input enabled */
+#define PIN_PDIS	(1 << 16) /* pull up/down disabled */
+#define PIN_PTU	(1 << 17) /* pull up */
+#define PIN_PTD	(0 << 17) /* pull down */
+
+#define MODE(m)	((m) & 0x7)
+#define MAX_PIN_N	260
+
+#define MUX_CFG(value, index)  \
+	__raw_writel(\
+		     (value) | \
+		     (__raw_readl(K2G_PADCFG_REG + (index << 2)) & \
+		      (0x3 << 19)),\
+		     (K2G_PADCFG_REG + (index << 2))\
+		    );
+
+struct pin_cfg {
+	int	reg_inx;
+	u32	val;
+};
+
+static inline void configure_pin_mux(struct pin_cfg *pin_mux)
+{
+	if (!pin_mux)
+		return;
+
+	while ((pin_mux->reg_inx >= 0) && (pin_mux->reg_inx < MAX_PIN_N)) {
+		MUX_CFG(pin_mux->val, pin_mux->reg_inx);
+		pin_mux++;
+	}
+}
+
+#endif /* __ASM_ARCH_MUX_K2G_H */
diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c
index a9a7d41160..aadd10bff2 100644
--- a/arch/arm/mach-keystone/init.c
+++ b/arch/arm/mach-keystone/init.c
@@ -103,7 +103,9 @@ int arch_cpu_init(void)
 
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
+#ifdef KS2_MSMC_SEGMENT_QM_PDSP
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
+#endif
 	msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
 
 	/* Initialize the PCIe-0 to work as Root Complex */
@@ -122,8 +124,10 @@ int arch_cpu_init(void)
 	 * UART register PWREMU_MGMT is initialized. Linux UART
 	 * driver doesn't handle this.
 	 */
+#ifndef CONFIG_DM_SERIAL
 	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
 		     CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+#endif
 
 	return 0;
 }
@@ -167,6 +171,9 @@ int print_cpuinfo(void)
 	case CPU_66AK2Ex:
 		puts("66AK2Ex SR");
 		break;
+	case CPU_66AK2Gx:
+		puts("66AK2Gx SR");
+		break;
 	default:
 		puts("Unknown\n");
 	}