diff options
author | mingming lee <mingming.lee@mediatek.com> | 2019-12-31 11:29:19 +0800 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-01-16 09:39:45 -0500 |
commit | 953bb4c3ce026395a2a4b9fb5e1fda79cde2fd97 (patch) | |
tree | 647d13c9cac927987abe913af5f0481b82a4093f /arch/arm/mach-mediatek/mt8512/init.c | |
parent | 0c0859cf2dae59932774c8034c8228d1b80368f1 (diff) |
ARM: MediaTek: Add support for MediaTek MT8512 SoC
Add support for MediaTek MT8512 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee <mingming.lee@mediatek.com>
Diffstat (limited to 'arch/arm/mach-mediatek/mt8512/init.c')
-rw-r--r-- | arch/arm/mach-mediatek/mt8512/init.c | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c new file mode 100644 index 0000000000..a38b5d12d9 --- /dev/null +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Configuration for MediaTek MT8512 SoC + * + * Copyright (C) 2019 MediaTek Inc. + * Author: Mingming Lee <mingming.lee@mediatek.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <wdt.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt8512-clk.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +phys_size_t get_effective_memsize(void) +{ + /* limit stack below tee reserve memory */ + return gd->ram_size - 6 * SZ_1M; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = get_effective_memsize(); + + return 0; +} + +void reset_cpu(ulong addr) +{ + struct udevice *watchdog_dev = NULL; + + if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) + if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) + psci_system_reset(); + + wdt_expire_now(watchdog_dev, 0); +} + +int print_cpuinfo(void) +{ + debug("CPU: MediaTek MT8512\n"); + return 0; +} + +static struct mm_region mt8512_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8512_mem_map; |