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| author | Ye Li <ye.li@nxp.com> | 2018-05-14 09:44:29 -0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2018-06-18 16:21:25 +0200 |
| commit | c5437e5b8aff9c952ebaab9be7670439c141e4e7 (patch) | |
| tree | f7c79c497e2159cea8306c7a0d343039b31e455a /arch/arm/mach-mvebu/timer.c | |
| parent | 2c09dbf4250be1f6c8fc391cc1882df35b47a421 (diff) | |
imx: Enable ACTLR.SMP bit for all i.MX cortex-a7 platforms
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure this bit
is set to 1 before the caches and MMU are enabled, or any cache and TLB
maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download mode,
it is not set.
Here we add it in u-boot as a common flow for all i.MX cortex-a7 platforms,
including mx7d, mx6ul/ull and mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
[fabio: adapted to U-Boot mainline codebase and make checkpatch happy]
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Diffstat (limited to 'arch/arm/mach-mvebu/timer.c')
0 files changed, 0 insertions, 0 deletions