diff options
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-10-31 15:06:50 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2018-11-02 15:57:13 +0100 |
| commit | e5cb6bd9a2db28338d3595bb3ea30f63624936d6 (patch) | |
| tree | 9be74259d29df83bd05b2a3a06353633eeb441cc /arch/arm/mach-rmobile/cpu_info.c | |
| parent | 5dbdd3a600906f56a19c9a82a741705988851a28 (diff) | |
ARM: rmobile: Generate fitting mem_map on Gen3
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire
64bit DRAM space as cachable. On CortexA57, this might result in odd
side effects, where the CPU tries to prefetch from those areas and if
there is no DRAM backing them, CPU bus hang can happen.
This patch fixes it by generating the mem_map structure based on the
actual memory layout obtained from the DT, thus not marking areas
without any DRAM behind them as cachable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Fixes: c1ec34763811d ("ARM: rmobile: Mark 4-64GiB as DRAM on Gen3")
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Diffstat (limited to 'arch/arm/mach-rmobile/cpu_info.c')
| -rw-r--r-- | arch/arm/mach-rmobile/cpu_info.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index e110737471..c9ebc9f40e 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -6,6 +6,8 @@ #include <common.h> #include <asm/io.h> +/* R-Car Gen3 caches are enabled in memmap-gen3.c */ +#ifndef CONFIG_RCAR_GEN3 #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { @@ -20,6 +22,7 @@ void enable_caches(void) dcache_enable(); } #endif +#endif #ifdef CONFIG_DISPLAY_CPUINFO static u32 __rmobile_get_cpu_type(void) |