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authorJeffy Chen <jeffy.chen@rock-chips.com>2015-11-17 14:20:29 +0800
committerSimon Glass <sjg@chromium.org>2015-12-01 08:07:22 -0700
commit6ae5860942f4eb053e9b8c7e2673eaa7d648082d (patch)
tree7694a565eb15215a7e57e5864016e26433fc72bb /arch/arm/mach-rockchip/Kconfig
parentd8b597823b90f43cb3cd1fb82ab1f4804a8ad1e5 (diff)
rockchip: Add max spl size & spl header configs
Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
Diffstat (limited to 'arch/arm/mach-rockchip/Kconfig')
-rw-r--r--arch/arm/mach-rockchip/Kconfig15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index a2069f878d..961a40264a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -17,6 +17,21 @@ config ROCKCHIP_RK3036
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+config ROCKCHIP_SPL_HDR
+ string "Header of rockchip's spl loader"
+ help
+ Rockchip's bootrom requires the spl loader to start with a 4-bytes
+ header. The content of this header depends on the chip type.
+
+config ROCKCHIP_MAX_SPL_SIZE
+ hex "Max size of rockchip's spl loader"
+ help
+ Different chip may have different sram size. And if we want to jump
+ back to the bootrom after spl, we may need to reserve some sram space
+ for the bootrom.
+ The max spl loader size should be sram size minus reserved
+ size(if needed)
+
config SYS_MALLOC_F
default y