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authorKever Yang <kever.yang@rock-chips.com>2016-07-29 10:35:25 +0800
committerSimon Glass <sjg@chromium.org>2016-08-05 17:56:07 -0600
commitb0b3c86521e0fe4cca3676adfc0b937d77456f9e (patch)
tree540c55a8983f35696e00e4e16faefbd9cf72f97d /arch/arm/mach-rockchip/rk3399
parent2918d96728379b544fd8ba397cdeb47170dc38f8 (diff)
rk3399: add basic soc driver
This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/mach-rockchip/rk3399')
-rw-r--r--arch/arm/mach-rockchip/rk3399/Makefile2
-rw-r--r--arch/arm/mach-rockchip/rk3399/reset_rk3399.c45
-rw-r--r--arch/arm/mach-rockchip/rk3399/syscon_rk3399.c20
3 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile
index 3f219ac6f8..3ca20284ef 100644
--- a/arch/arm/mach-rockchip/rk3399/Makefile
+++ b/arch/arm/mach-rockchip/rk3399/Makefile
@@ -5,3 +5,5 @@
#
obj-y += rk3399.o
+obj-y += reset_rk3399.o
+obj-y += syscon_rk3399.o
diff --git a/arch/arm/mach-rockchip/rk3399/reset_rk3399.c b/arch/arm/mach-rockchip/rk3399/reset_rk3399.c
new file mode 100644
index 0000000000..9a555464c6
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/reset_rk3399.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3399.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk3399_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(0xeca8, &cru->glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ writel(0xfdb9, &cru->glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk3399_sysreset = {
+ .request = rk3399_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk3399) = {
+ .name = "rk3399_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk3399_sysreset,
+};
diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
new file mode 100644
index 0000000000..2d81c55cd2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
@@ -0,0 +1,20 @@
+/*
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3399_syscon_ids[] = {
+ { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF },
+};
+
+U_BOOT_DRIVER(syscon_rk3399) = {
+ .name = "rk3399_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3399_syscon_ids,
+};