diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2019-11-15 11:04:35 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-11-17 16:23:56 +0800 |
| commit | 9a46f2a4cb1bfcddef1379e41a710d352b2dade0 (patch) | |
| tree | ce542d842b4a666b6dcf4520f19cab714dfd6484 /arch/arm/mach-rockchip/sdram.c | |
| parent | d5d40f45ded050f9d641d71fb29a5afe90f42700 (diff) | |
rockchip: sdram: extend to use sys_reg3 for capacity info
Since we have new DRAM type and to support different DRAM size in different
CS, we need more bits, so introduce sys_reg3 to record the info.
Note that the info in sys_reg3 is extension to sys_reg2 and the info in
sys_reg2 is the same as before. We define the DRAM_INFO with sys_reg3 as
VERSION2.
All the ENC macro are moved to sdram_common.h since the sdram.c only
need to do the info decode.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/mach-rockchip/sdram.c')
| -rw-r--r-- | arch/arm/mach-rockchip/sdram.c | 69 |
1 files changed, 59 insertions, 10 deletions
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index acb1af765e..8e5a572dba 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -76,39 +76,88 @@ int dram_init_banksize(void) size_t rockchip_sdram_size(phys_addr_t reg) { - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; size_t chipsize_mb = 0; size_t size_mb = 0; u32 ch; - + u32 cs1_col = 0; + u32 bg = 0; + u32 dbw, dram_type; u32 sys_reg = readl(reg); + u32 sys_reg3 = readl(reg + 4); u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); + dram_type = (sys_reg >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK; debug("%s %x %x\n", __func__, (u32)reg, sys_reg); for (ch = 0; ch < ch_num; ch++) { rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + cs0_col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & + SYS_REG_COL_MASK); + cs1_col = cs0_col; bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & + SYS_REG_VERSION_MASK) == 0x2) { + cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) & + SYS_REG_CS1_COL_MASK); + if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & + SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg >> + SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK) == 7) + cs0_row = 12; + else + cs0_row = 13 + (sys_reg >> + SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK) + + ((sys_reg3 >> + SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & + SYS_REG_EXTEND_CS0_ROW_MASK) << 2); + if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) & + SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg >> + SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK) == 7) + cs1_row = 12; + else + cs1_row = 13 + (sys_reg >> + SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK) + + ((sys_reg3 >> + SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) & + SYS_REG_EXTEND_CS1_ROW_MASK) << 2); + } else { + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK); + } bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & SYS_REG_BW_MASK)); row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; - - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + if (dram_type == DDR4) { + dbw = (sys_reg >> SYS_REG_DBW_SHIFT(ch)) & + SYS_REG_DBW_MASK; + bg = (dbw == 2) ? 2 : 1; + } + chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); if (rank > 1) - chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); + chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + + (cs0_col - cs1_col)); if (row_3_4) chipsize_mb = chipsize_mb * 3 / 4; size_mb += chipsize_mb; - debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", - rank, col, bk, cs0_row, bw, row_3_4); + if (rank > 1) + debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\ + cs1_row %d bw %d row_3_4 %d\n", + rank, cs0_col, cs1_col, bk, cs0_row, + cs1_row, bw, row_3_4); + else + debug("rank %d cs0_col %d bk %d cs0_row %d\ + bw %d row_3_4 %d\n", + rank, cs0_col, bk, cs0_row, + bw, row_3_4); } /* |