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authorMinkyu Kang <mk7.kang@samsung.com>2015-11-20 15:24:57 +0900
committerMinkyu Kang <mk7.kang@samsung.com>2015-11-30 17:17:01 +0900
commit225f5eeccd6c0d376a20c15897edd8c69500d8cc (patch)
treef1348e316a9c4b871d3cadbab9d9cdbe7ce5852a /arch/arm/mach-s5pc1xx/include/mach/mmc.h
parentfa8883a1e39a20e72aaa5093af0c80062cb95757 (diff)
arm: s5pc1xx: move SoC to mach-s5pc1xx
move arm/arm/cpu/armv7/s5pc1xx to arch/arm/mach-s5pc1xx Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/mach-s5pc1xx/include/mach/mmc.h')
-rw-r--r--arch/arm/mach-s5pc1xx/include/mach/mmc.h65
1 files changed, 65 insertions, 0 deletions
diff --git a/arch/arm/mach-s5pc1xx/include/mach/mmc.h b/arch/arm/mach-s5pc1xx/include/mach/mmc.h
new file mode 100644
index 0000000000..dd473c8ecd
--- /dev/null
+++ b/arch/arm/mach-s5pc1xx/include/mach/mmc.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#define S5P_MMC_DEV_OFFSET 0x100000
+
+#define SDHCI_CONTROL2 0x80
+#define SDHCI_CONTROL3 0x84
+#define SDHCI_CONTROL4 0x8C
+
+#define SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31)
+#define SDHCI_CTRL2_ENCMDCNFMSK (1 << 30)
+#define SDHCI_CTRL2_CDINVRXD3 (1 << 29)
+#define SDHCI_CTRL2_SLCARDOUT (1 << 28)
+
+#define SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24)
+#define SDHCI_CTRL2_FLTCLKSEL_SHIFT (24)
+#define SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24)
+
+#define SDHCI_CTRL2_LVLDAT_MASK (0xff << 16)
+#define SDHCI_CTRL2_LVLDAT_SHIFT (16)
+#define SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16)
+
+#define SDHCI_CTRL2_ENFBCLKTX (1 << 15)
+#define SDHCI_CTRL2_ENFBCLKRX (1 << 14)
+#define SDHCI_CTRL2_SDCDSEL (1 << 13)
+#define SDHCI_CTRL2_SDSIGPC (1 << 12)
+#define SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11)
+
+#define SDHCI_CTRL2_DFCNT_MASK(_x) ((_x) << 9)
+#define SDHCI_CTRL2_DFCNT_SHIFT (9)
+
+#define SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8)
+#define SDHCI_CTRL2_RWAITMODE (1 << 7)
+#define SDHCI_CTRL2_DISBUFRD (1 << 6)
+#define SDHCI_CTRL2_SELBASECLK_MASK(_x) ((_x) << 4)
+#define SDHCI_CTRL2_SELBASECLK_SHIFT (4)
+#define SDHCI_CTRL2_PWRSYNC (1 << 3)
+#define SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1)
+#define SDHCI_CTRL2_HWINITFIN (1 << 0)
+
+#define SDHCI_CTRL3_FCSEL3 (1 << 31)
+#define SDHCI_CTRL3_FCSEL2 (1 << 23)
+#define SDHCI_CTRL3_FCSEL1 (1 << 15)
+#define SDHCI_CTRL3_FCSEL0 (1 << 7)
+
+#define SDHCI_CTRL4_DRIVE_MASK(_x) ((_x) << 16)
+#define SDHCI_CTRL4_DRIVE_SHIFT (16)
+
+int s5p_sdhci_init(u32 regbase, int index, int bus_width);
+
+static inline int s5p_mmc_init(int index, int bus_width)
+{
+ unsigned int base = samsung_get_base_mmc() +
+ (S5P_MMC_DEV_OFFSET * index);
+
+ return s5p_sdhci_init(base, index, bus_width);
+}
+#endif