diff options
| author | Ramon Fried <ramon.fried@gmail.com> | 2018-05-16 12:13:39 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-05-26 18:19:11 -0400 |
| commit | 640dc349422d1f228ef8d2bb35cd89b1663273f1 (patch) | |
| tree | f195699e78d77164749bc509e47101e49072ea79 /arch/arm/mach-snapdragon/clock-apq8096.c | |
| parent | 7e5ad796bcd65772a87da236ae21cd536ae3a4d2 (diff) | |
mach-snapdragon: Fix UART clock flow
UART clock enabling flow was wrong.
Changed the flow according to downstream implementation in LK.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Diffstat (limited to 'arch/arm/mach-snapdragon/clock-apq8096.c')
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-apq8096.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index 008649a4c6..628c38785b 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -27,7 +27,7 @@ static const struct bcr_regs sdc_regs = { .D = SDCC2_D, }; -static const struct gpll0_ctrl gpll0_ctrl = { +static const struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, .ena_vote = APCS_GPLL_ENA_VOTE, @@ -41,7 +41,7 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) clk_enable_cbc(priv->base + SDCC2_AHB_CBCR); clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0, CFG_CLK_SRC_GPLL0); - clk_enable_gpll0(priv->base, &gpll0_ctrl); + clk_enable_gpll0(priv->base, &gpll0_vote_clk); clk_enable_cbc(priv->base + SDCC2_APPS_CBCR); return rate; |