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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2019-09-04 06:25:44 +0000 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2019-09-12 16:15:42 +0530 |
| commit | 116f75c7b310bb5087195416e309d5a292e04560 (patch) | |
| tree | 53fd86aa38d28853e8c351cc2d96ed4be5bba36a /arch/arm/mach-snapdragon/include | |
| parent | c9ba88bafc786a258f64ce673fc63b9e5994c88a (diff) | |
armv8: ls1028a: Updated serdes configuration for 0x13BB
In SerDes protocol 0x13BB, lane C was erroneously assigned
to PCIE1, this is now updated to PCIE2
Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes
protocal support")
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/mach-snapdragon/include')
0 files changed, 0 insertions, 0 deletions