diff options
author | Tom Rini <trini@konsulko.com> | 2019-01-26 22:47:55 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2019-01-26 22:47:55 -0500 |
commit | 0da90255083681a02b24528f80da9d4062ff634a (patch) | |
tree | 3046fb2c4824adaf891d0356e024da0dd0b2398f /arch/arm/mach-snapdragon | |
parent | 87f78478a4a1bf574db0b0e575ca37cf91fb187c (diff) | |
parent | 320194ae35801811bd7754f23ac04bd841d25aa3 (diff) |
Merge branch '2019-01-25-master-imports'
- snapdragon 820c improvements
- poplar updates
- DFU + SPL cleanups
- Improve the mediatek mmc driver
- Other minor cleanups / improvements
Diffstat (limited to 'arch/arm/mach-snapdragon')
-rw-r--r-- | arch/arm/mach-snapdragon/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/clock-apq8096.c | 34 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-apq8096.c | 56 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 |
6 files changed, 106 insertions, 5 deletions
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 2d94083600..709919fce4 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -6,8 +6,9 @@ obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-apq8016.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += pinctrl-snapdragon.o obj-y += misc.o obj-y += clock-snapdragon.o obj-y += dram.o +obj-y += pinctrl-snapdragon.o +obj-y += pinctrl-apq8016.o +obj-y += pinctrl-apq8096.o diff --git a/arch/arm/mach-snapdragon/clock-apq8096.c b/arch/arm/mach-snapdragon/clock-apq8096.c index 628c38785b..e5011be8f2 100644 --- a/arch/arm/mach-snapdragon/clock-apq8096.c +++ b/arch/arm/mach-snapdragon/clock-apq8096.c @@ -34,6 +34,12 @@ static const struct pll_vote_clk gpll0_vote_clk = { .vote_bit = APCS_GPLL_ENA_VOTE_GPLL0, }; +static struct vote_clk gcc_blsp2_ahb_clk = { + .cbcr_reg = BLSP2_AHB_CBCR, + .ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE, + .vote_bit = BIT(15), +}; + static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) { int div = 3; @@ -47,6 +53,32 @@ static int clk_init_sdc(struct msm_clk_priv *priv, uint rate) return rate; } +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = BLSP2_UART2_APPS_CFG_RCGR, + .cmd_rcgr = BLSP2_UART2_APPS_CMD_RCGR, + .M = BLSP2_UART2_APPS_M, + .N = BLSP2_UART2_APPS_N, + .D = BLSP2_UART2_APPS_D, +}; + +static int clk_init_uart(struct msm_clk_priv *priv) +{ + /* Enable AHB clock */ + clk_enable_vote_clk(priv->base, &gcc_blsp2_ahb_clk); + + /* 7372800 uart block clock @ GPLL0 */ + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 1, 192, 15625, + CFG_CLK_SRC_GPLL0); + + /* Vote for gpll0 clock */ + clk_enable_gpll0(priv->base, &gpll0_vote_clk); + + /* Enable core clk */ + clk_enable_cbc(priv->base + BLSP2_UART2_APPS_CBCR); + + return 0; +} + ulong msm_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -55,6 +87,8 @@ ulong msm_set_rate(struct clk *clk, ulong rate) case 0: /* SDC1 */ return clk_init_sdc(priv, rate); break; + case 4: /*UART2*/ + return clk_init_uart(priv); default: return 0; } diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h index 14febb6487..36a902bd92 100644 --- a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h @@ -15,6 +15,7 @@ /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x0000) #define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) #define SDCC2_BCR (0x14000) /* block reset */ #define SDCC2_APPS_CBCR (0x14004) /* branch control */ @@ -25,4 +26,12 @@ #define SDCC2_N (0x1401C) #define SDCC2_D (0x14020) +#define BLSP2_AHB_CBCR (0x25004) +#define BLSP2_UART2_APPS_CBCR (0x29004) +#define BLSP2_UART2_APPS_CMD_RCGR (0x2900C) +#define BLSP2_UART2_APPS_CFG_RCGR (0x29010) +#define BLSP2_UART2_APPS_M (0x29014) +#define BLSP2_UART2_APPS_N (0x29018) +#define BLSP2_UART2_APPS_D (0x2901C) + #endif diff --git a/arch/arm/mach-snapdragon/pinctrl-apq8096.c b/arch/arm/mach-snapdragon/pinctrl-apq8096.c new file mode 100644 index 0000000000..20a71c319b --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-apq8096.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm APQ8096 pinctrl + * + * (C) Copyright 2019 Ramon Fried <ramon.fried@gmail.com> + * + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN]; +static const char * const msm_pinctrl_pins[] = { + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", + "SDC1_RCLK", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart8", 2}, +}; + +static const char *apq8096_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *apq8096_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 150) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 150]; + } +} + +static unsigned int apq8096_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data apq8096_data = { + .pin_count = 157, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = apq8096_get_function_name, + .get_function_mux = apq8096_get_function_mux, + .get_pin_name = apq8096_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index 5365ccdb70..9ba8fdd729 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -22,7 +22,7 @@ struct msm_pinctrl_priv { #define TLMM_GPIO_PULL_MASK GENMASK(1, 0) #define TLMM_FUNC_SEL_MASK GENMASK(5, 2) #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_ENABLE BIT(9) +#define TLMM_GPIO_DISABLE BIT(9) static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 }, @@ -74,7 +74,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, struct msm_pinctrl_priv *priv = dev_get_priv(dev); clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE, + TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, priv->data->get_function_mux(func_selector) << 2); return 0; } @@ -113,8 +113,8 @@ static struct pinctrl_ops msm_pinctrl_ops = { }; static const struct udevice_id msm_pinctrl_ids[] = { - { .compatible = "qcom,tlmm-msm8916", .data = (ulong)&apq8016_data }, { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, + { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index c47d988af4..24f8863f59 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -26,5 +26,6 @@ struct pinctrl_function { }; extern struct msm_pinctrl_data apq8016_data; +extern struct msm_pinctrl_data apq8096_data; #endif |