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authorLey Foon Tan <ley.foon.tan@intel.com>2017-04-26 02:44:48 +0800
committerMarek Vasut <marex@denx.de>2017-05-18 11:33:19 +0200
commitd89e979c42892db572c4ef5d56bc207075953f58 (patch)
tree497806ec47a6c1bf620303829cdb095374e55f76 /arch/arm/mach-socfpga/Kconfig
parent9b21de78116ccb4c47dc82daae9598e19060f669 (diff)
arm: socfpga: Enable build for Arria 10
Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/Kconfig')
-rw-r--r--arch/arm/mach-socfpga/Kconfig10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index f6e5773272..2563e7926d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -37,6 +37,9 @@ config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
+config TARGET_SOCFPGA_ARRIA10
+ bool
+
config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
@@ -49,6 +52,10 @@ choice
prompt "Altera SOCFPGA board select"
optional
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+ bool "Altera SOCFPGA SoCDK (Arria 10)"
+ select TARGET_SOCFPGA_ARRIA10
+
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
@@ -98,6 +105,7 @@ endchoice
config SYS_BOARD
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
@@ -111,6 +119,7 @@ config SYS_BOARD
config SYS_VENDOR
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -125,6 +134,7 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC