diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2017-04-26 02:44:33 +0800 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2017-05-18 11:33:16 +0200 |
| commit | de7781158923a9c87debc5a89ce4fabfd0fc93bc (patch) | |
| tree | 2f688d87f0559d5c19d48f633681abffd10d5f52 /arch/arm/mach-socfpga/Makefile | |
| parent | fa8967cfbaed5582ba987756fa9f0470a9affbf4 (diff) | |
arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.
- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
cm_write_with_phase() and cm_basic_init().
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/Makefile')
| -rw-r--r-- | arch/arm/mach-socfpga/Makefile | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 809cd47947..b76de4c54d 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -13,7 +13,8 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o # QTS-generated config file wrappers -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \ + clock_manager_gen5.o obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ wrap_sdram_config.o CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) |