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authorMarek Vasut <marex@denx.de>2018-08-06 21:42:05 +0200
committerMarek Vasut <marex@denx.de>2018-08-13 22:35:42 +0200
commitd81b5da3fef726f645132e1b84caed7b6e34020f (patch)
tree73066497c89b828e891471a221df020956b582c9 /arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
parent12ea13ad4348bc650c33ebcfb7ed34af634b5ab7 (diff)
ARM: socfpga: clk: Convert to clock framework
Use clock framework functions to fetch clock information now that there is a clock driver for Arria10, instead of custom coded register parsing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h')
-rw-r--r--arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index cb2306e5bc..b3c8853aa3 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -90,18 +90,12 @@ struct socfpga_clock_manager {
};
void cm_use_intosc(void);
-unsigned int cm_get_noc_clk_hz(void);
-unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift);
int cm_basic_init(const void *blob);
unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned int cm_get_main_vco_clk_hz(void);
-unsigned int cm_get_per_vco_clk_hz(void);
unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
-unsigned int cm_get_mmc_controller_clk_hz(void);
-unsigned int cm_get_spi_controller_clk_hz(void);
#endif /* __ASSEMBLER__ */