diff options
| author | Marek Vasut <marex@denx.de> | 2015-08-02 18:12:08 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2015-08-08 14:14:29 +0200 |
| commit | d718a26b0c2b6ee869070386fea0ad68a3031987 (patch) | |
| tree | 55abeaf3e6e7b87313eed13d0c7ea33909766896 /arch/arm/mach-socfpga/include/mach | |
| parent | 04955cf247cc75cc08c4667f785e74a2435f5061 (diff) | |
ddr: altera: sequencer: Wrap RW_MGR_* macros
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/sdram.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 901cd9b5e4..eb409348c3 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -16,6 +16,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void); void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem); void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem); +const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void); #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) @@ -116,6 +117,69 @@ struct socfpga_sdram_config { u32 phy_ctrl0; }; +struct socfpga_sdram_rw_mgr_config { + u8 activate_0_and_1; + u8 activate_0_and_1_wait1; + u8 activate_0_and_1_wait2; + u8 activate_1; + u8 clear_dqs_enable; + u8 guaranteed_read; + u8 guaranteed_read_cont; + u8 guaranteed_write; + u8 guaranteed_write_wait0; + u8 guaranteed_write_wait1; + u8 guaranteed_write_wait2; + u8 guaranteed_write_wait3; + u8 idle; + u8 idle_loop1; + u8 idle_loop2; + u8 init_reset_0_cke_0; + u8 init_reset_1_cke_0; + u8 lfsr_wr_rd_bank_0; + u8 lfsr_wr_rd_bank_0_data; + u8 lfsr_wr_rd_bank_0_dqs; + u8 lfsr_wr_rd_bank_0_nop; + u8 lfsr_wr_rd_bank_0_wait; + u8 lfsr_wr_rd_bank_0_wl_1; + u8 lfsr_wr_rd_dm_bank_0; + u8 lfsr_wr_rd_dm_bank_0_data; + u8 lfsr_wr_rd_dm_bank_0_dqs; + u8 lfsr_wr_rd_dm_bank_0_nop; + u8 lfsr_wr_rd_dm_bank_0_wait; + u8 lfsr_wr_rd_dm_bank_0_wl_1; + u8 mrs0_dll_reset; + u8 mrs0_dll_reset_mirr; + u8 mrs0_user; + u8 mrs0_user_mirr; + u8 mrs1; + u8 mrs1_mirr; + u8 mrs2; + u8 mrs2_mirr; + u8 mrs3; + u8 mrs3_mirr; + u8 precharge_all; + u8 read_b2b; + u8 read_b2b_wait1; + u8 read_b2b_wait2; + u8 refresh_all; + u8 rreturn; + u8 sgle_read; + u8 zqcl; + + u8 true_mem_data_mask_width; + u8 mem_address_mirroring; + u8 mem_data_mask_width; + u8 mem_data_width; + u8 mem_dq_per_read_dqs; + u8 mem_dq_per_write_dqs; + u8 mem_if_read_dqs_width; + u8 mem_if_write_dqs_width; + u8 mem_number_of_cs_per_dimm; + u8 mem_number_of_ranks; + u8 mem_virtual_groups_per_read_dqs; + u8 mem_virtual_groups_per_write_dqs; +}; + #define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 #define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 #define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 |