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authorMarek Vasut <marex@denx.de>2015-08-02 19:00:23 +0200
committerMarek Vasut <marex@denx.de>2015-08-08 14:14:29 +0200
commit10c14261f3c0644d2ae21785701f5aa3898d98e9 (patch)
treeeb9b939cfeecbfc8ca007c891db3e246b5cf9e4f /arch/arm/mach-socfpga/include
parent1fa0c8c4e30c4aae67b79263c749a66a67d42e5e (diff)
ddr: altera: sequencer: Wrap IO_* macros
Introduce structure socfpga_sdram_io_config to wrap the IO configuration values in board file. Introduce socfpga_get_sdram_io_config() function, which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include')
-rw-r--r--arch/arm/mach-socfpga/include/mach/sdram.h19
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index eb409348c3..9d0e0833e5 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -17,6 +17,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
+const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void);
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
@@ -180,6 +181,24 @@ struct socfpga_sdram_rw_mgr_config {
u8 mem_virtual_groups_per_write_dqs;
};
+struct socfpga_sdram_io_config {
+ u16 delay_per_opa_tap;
+ u8 delay_per_dchain_tap;
+ u8 delay_per_dqs_en_dchain_tap;
+ u8 dll_chain_length;
+ u8 dqdqs_out_phase_max;
+ u8 dqs_en_delay_max;
+ u8 dqs_en_delay_offset;
+ u8 dqs_en_phase_max;
+ u8 dqs_in_delay_max;
+ u8 dqs_in_reserve;
+ u8 dqs_out_reserve;
+ u8 io_in_delay_max;
+ u8 io_out1_delay_max;
+ u8 io_out2_delay_max;
+ u8 shift_dqs_en_when_shift_dqs;
+};
+
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22