diff options
| author | Ang, Chee Hong <chee.hong.ang@intel.com> | 2019-05-03 01:19:08 -0700 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-05-06 12:44:45 +0200 |
| commit | a03e9d9fe5e2645be1c053b2765cfe6a9126d362 (patch) | |
| tree | 7bd7bbed5c8f5dbbee3934e8484a22f7c89b4248 /arch/arm/mach-socfpga/include | |
| parent | 6bf238a46192bf9164da4548178d657dde4e1c96 (diff) | |
ARM: socfpga: stratix10: Disable FPGA2SOC reset
Software must never reset FPGA2SOC bridge. This bridge must only be
reset by POR/COLD/WARM reset. Asserting the FPGA2SOC reset by software
can cause the SoC to lock-up if there are traffics being drived into
FPGA2SOC bridge.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/reset_manager_s10.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h index e186296791..b93bbaf537 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -48,6 +48,8 @@ struct socfpga_reset_manager { #define RSTMGR_MPUMODRST_CORE0 0 #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 #define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + /* Watchdogs and MPU warm reset mask */ #define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 |