arm: socfpga: Convert reset manager from struct to defines

Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.

Change to get reset manager base address from DT node instead of using
#define.

spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

5 files changed, 26 insertions, 75 deletions

diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index f11f907e1c..f6de1ccb4a 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
 
 void do_bridge_reset(int enable, unsigned int mask);
 void socfpga_pl310_clear(void);
+void socfpga_get_managers_addr(void);
 
 #endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6ad037e325..96052d94b4 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -6,6 +6,8 @@
 #ifndef _RESET_MANAGER_H_
 #define _RESET_MANAGER_H_
 
+phys_addr_t socfpga_get_rstmgr_addr(void);
+
 void reset_cpu(ulong addr);
 
 void socfpga_per_reset(u32 reset, int set);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 6623ebee65..22e4eb33de 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_deassert_osc1wd0(void);
 int socfpga_bridges_reset(void);
 
-struct socfpga_reset_manager {
-	u32	stat;
-	u32	ramstat;
-	u32	miscstat;
-	u32	ctrl;
-	u32	hdsken;
-	u32	hdskreq;
-	u32	hdskack;
-	u32	counts;
-	u32	mpumodrst;
-	u32	per0modrst;
-	u32	per1modrst;
-	u32	brgmodrst;
-	u32	sysmodrst;
-	u32	coldmodrst;
-	u32	nrstmodrst;
-	u32	dbgmodrst;
-	u32	mpuwarmmask;
-	u32	per0warmmask;
-	u32	per1warmmask;
-	u32	brgwarmmask;
-	u32	syswarmmask;
-	u32	nrstwarmmask;
-	u32	l3warmmask;
-	u32	tststa;
-	u32	tstscratch;
-	u32	hdsktimeout;
-	u32	hmcintr;
-	u32	hmcintren;
-	u32	hmcintrens;
-	u32	hmcintrenr;
-	u32	hmcgpout;
-	u32	hmcgpin;
-};
+#define RSTMGR_A10_STATUS	0x00
+#define RSTMGR_A10_CTRL		0x0c
+#define RSTMGR_A10_MPUMODRST	0x20
+#define RSTMGR_A10_PER0MODRST	0x24
+#define RSTMGR_A10_PER1MODRST	0x28
+#define RSTMGR_A10_BRGMODRST	0x2c
+#define RSTMGR_A10_SYSMODRST	0x30
+
+#define RSTMGR_CTRL		RSTMGR_A10_CTRL
 
 /*
  * SocFPGA Arria10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index f4dcb14623..d108eac1e2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -11,19 +11,15 @@
 void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
 void socfpga_bridges_reset(int enable);
 
-struct socfpga_reset_manager {
-	u32	status;
-	u32	ctrl;
-	u32	counts;
-	u32	padding1;
-	u32	mpu_mod_reset;
-	u32	per_mod_reset;
-	u32	per2_mod_reset;
-	u32	brg_mod_reset;
-	u32	misc_mod_reset;
-	u32	padding2[12];
-	u32	tstscratch;
-};
+#define RSTMGR_GEN5_STATUS	0x00
+#define RSTMGR_GEN5_CTRL	0x04
+#define RSTMGR_GEN5_MPUMODRST	0x10
+#define RSTMGR_GEN5_PERMODRST	0x14
+#define RSTMGR_GEN5_PER2MODRST	0x18
+#define RSTMGR_GEN5_BRGMODRST	0x1c
+#define RSTMGR_GEN5_MISCMODRST	0x20
+
+#define RSTMGR_CTRL		RSTMGR_GEN5_CTRL
 
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 452147b017..611f7efa6e 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -15,34 +15,11 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
-struct socfpga_reset_manager {
-	u32	status;
-	u32	mpu_rst_stat;
-	u32	misc_stat;
-	u32	padding1;
-	u32	hdsk_en;
-	u32	hdsk_req;
-	u32	hdsk_ack;
-	u32	hdsk_stall;
-	u32	mpumodrst;
-	u32	per0modrst;
-	u32	per1modrst;
-	u32	brgmodrst;
-	u32	padding2;
-	u32     cold_mod_reset;
-	u32	padding3;
-	u32     dbg_mod_reset;
-	u32     tap_mod_reset;
-	u32	padding4;
-	u32	padding5;
-	u32     brg_warm_mask;
-	u32	padding6[3];
-	u32     tst_stat;
-	u32	padding7;
-	u32     hdsk_timeout;
-	u32     mpul2flushtimeout;
-	u32     dbghdsktimeout;
-};
+#define RSTMGR_S10_STATUS	0x00
+#define RSTMGR_S10_MPUMODRST	0x20
+#define RSTMGR_S10_PER0MODRST	0x24
+#define RSTMGR_S10_PER1MODRST	0x28
+#define RSTMGR_S10_BRGMODRST	0x2c
 
 #define RSTMGR_MPUMODRST_CORE0		0
 #define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00